Delay locked loop for high speed semiconductor memory device

Details Delay locked loop for high speed semiconductor memory device Delay locked loop for high speed semiconductor memory device

2011-08-09

2011-08-09

Cox, Cassandra (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S149000

Reexamination Certificate

active

07994833

ABSTRACT:
A semiconductor device comprises a delay locked loop (DLL) configured to control a phase delay of an internal clock to output first and second DLL clocks; an output enable unit configured to generate rising/falling data output enable signals in response to the second DLL clocks; and an output driver configured to output data in response to one of the first DLL clocks selected by the rising/falling data output enable signals, where a phase of the second DLL clock leads that of the first DLL clock.

REFERENCES:
patent: 6859404 (2005-02-01), Kim
patent: 7173878 (2007-02-01), Kim
patent: 7298189 (2007-11-01), Kang et al.
patent: 7511546 (2009-03-01), Koo
patent: 7777542 (2010-08-01), Ku
patent: 2002/0015338 (2002-02-01), Lee
patent: 2002/0097074 (2002-07-01), Kim et al.
patent: 1474413 (2004-02-01), None
patent: 1497605 (2004-05-01), None
Notice of Allowance issued from Chinese State Intellectual Property Office on May 12, 2010.

Affiliated with

Also associated with

Rating

Delay locked loop for high speed semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Delay locked loop for high speed semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Delay locked loop for high speed semiconductor memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2656285