Delay locked loop for controlling duty rate of clock

Details Delay locked loop for controlling duty rate of clock Delay locked loop for controlling duty rate of clock

2008-05-13

2008-05-13

Richards, N. Drew (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S156000, C327S175000

Reexamination Certificate

active

07372311

ABSTRACT:
There is provided a DLL capable of controlling a duty rate of a clock by a fuse option or an EMRS input. The DLL includes a first clock buffer, a second clock buffer, a first delay line, a second delay line, a shift register, a first duty control unit, a second duty control unit, a first DLL driver, a second DLL driver, a delay model, a phase comparator, and a shift control unit. In the DLL, a first duty control unit and a second duty control unit control each duty rate of the output clocks of a first and a second delay lines respectively through the EMRS input or the fuse option. Therefore, it is possible to control the duty rate of DLL clocks through the EMRS input or the fuse option.

REFERENCES:
patent: 5614855 (1997-03-01), Lee et al.
patent: 6100733 (2000-08-01), Dortu et al.
patent: 6373309 (2002-04-01), Bang
patent: 6539072 (2003-03-01), Donnelly et al.
patent: 6677792 (2004-01-01), Kwak
patent: 6703879 (2004-03-01), Okuda et al.
patent: 6768361 (2004-07-01), Kwak
patent: 6853225 (2005-02-01), Lee
patent: 6859081 (2005-02-01), Hong et al.
patent: 6895522 (2005-05-01), Johnson et al.
patent: 7161397 (2007-01-01), Lee et al.
patent: 7279946 (2007-10-01), Minzoni
patent: 2003/0219088 (2003-11-01), Kwak
patent: 2007/0046346 (2007-03-01), Minzoni
patent: 2007/0069782 (2007-03-01), Shin
patent: 11-110065 (1999-04-01), None
patent: 2003-347908 (2003-12-01), None
patent: 2004-064735 (2004-02-01), None
patent: 2004-129255 (2004-04-01), None
patent: 2003-0052361 (2003-06-01), None
patent: 2003-0052650 (2003-06-01), None
patent: 10-2004-0020990 (2004-03-01), None
patent: 2004-0037786 (2004-05-01), None

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