Delay locked loop driver

Details Delay locked loop driver Delay locked loop driver

2000-02-21

2001-11-06

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S278000, C327S156000, C327S157000

Reexamination Certificate

active

06313675

ABSTRACT:

TECHNICAL FIELD
The present invention generally relates to the field of integrated circuit design. In particular, the present invention relates to delay locked loops and delay line circuits.
BACKGROUND
Delay lock loops (“DLL” s) are a commonly-used technology in integrated circuits. For a description of conventional DLL technology, reference may be made to the IEEE Journal of Solid State Circuits, Vol. 31, No. 11, 11/96. DLL circuits are used in many applications such as in clock drivers and input/output devices. DLL clock drivers can provide a controllably delayed clock output from an input reference clock signal. Such DLL (or similarly, Phase Lock Loops, PLL) clock drivers are ubiquitous in integrated circuit designs. In some applications, they include multi-stage delay lines with selectable taps from the various delay stages to allow the device to generate an output having preselected delay from a range of selectable delays from the input reference clock. With such DLL driver circuits, important performance parameters include low jitter (supply noise rejection), consistent performance within the operational environment, and delay accuracy.
FIG. 1
shows a circuit block diagram of a conventional DLL driver
50
. DLL driver
50
includes phase comparator
55
, charge pump
60
, buffer
65
, voltage controlled delay (“VCD”)
70
, and current source
75
. The VCD
70
generates a Delayed Ref. Clock signal
71
that is delayed from an input Ref. Clock signal
57
by an amount based on a Delay Select input
73
at the VCD
70
. The phase comparator
55
compares the phase difference between Reference Clock
57
and a Delay Feedback signal
77
. Based on this phase difference, the phase comparator
55
causes the charge pump to either increase or decrease its generated output control voltage V
ctl
, which is buffered at buffer
65
to produce a buffered control voltage V
bctl
that causes the VCD to either increase or decrease the phase of Delay Feedback
77
to force its phase to be locked with Ref. Clk.
57
. The Delayed Ref. Clk. signal
71
is generated from this Delay Feedback signal
77
and thus, it too becomes phase locked with Ref Clk.
57
and delayed from it by a preselected quantity. In this manner, a Delayed Ref. Clock signal is produced with a preselected, fixed delay from the Reference Clock input. Buffer
65
is needed to ensure that the charge pump's output control voltage Vctl is not affected by changes in the VCD's supply current needs. The current source
75
(and/or buffer
65
—they may be one in the same) provide the VCD
70
with its operating current. With buffer
65
responding to changes in the current demand of VCD
70
, a substantially fixed amount of current is provided to it. For reducing jitter, filtered supply voltages may be used for any or all of the component blocks.
Unfortunately, such conventional DLL drivers tend to be large in terms of their aggregate size relative to the other components within an IC device. Among other reasons, this can be attributed to VCD circuits that consume relatively large amounts of current, robust phase comparator/charge pump configurations, and large capacitors that are needed to sufficiently filter the various filtered voltage supplies. Large current consumption is generally an ancillary characteristic of a VCD that produces a signal with an accurate absolute delay from the reference signal. Such delay circuits require robust current sources and large capacitors for adequate filtering.
Accordingly, what is needed is an improved, more efficient DLL and/or delay line circuit design.
SUMMARY OF THE INVENTION
The present invention provides an improved, efficient DLL design. In one embodiment, it includes a voltage controlled delay line, a phase comparator, and a dynamic bias source. The delay line has an associated delay that is controllably adjusted by a received control signal. The delay line also has an input for receiving a reference signal and one or more outputs for providing one or more delayed versions of the reference signal. The phase comparator is operably connected to the delay line in a closed loop fashion for controlling the control signal based on the phase difference between the reference signal and one of the one or more delayed reference signal versions to cause the delay line to generate an output delayed reference signal that is in synch with the reference signal but delayed from it by a predetermined quantity. The dynamic bias source provides power to the delay line as it is needed so that the control signal is not adversely affected by changes in the delay line's power demands.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.


REFERENCES:
patent: 5973524 (1999-10-01), Martin
patent: 6150887 (2000-11-01), Yamaguchi

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