Delay locked loop (DLL) using an oscillator and a counter...

Details Delay locked loop (DLL) using an oscillator and a counter... Delay locked loop (DLL) using an oscillator and a counter...

2006-11-28

2006-11-28

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S149000, C327S161000

Reexamination Certificate

active

07142027

ABSTRACT:
Provided are a delay locked loop (DLL) using an oscillator and a counter and a clock synchronizing method. The DLL converts cycle information of an input clock signal into digital information using the oscillator and the counter and generates output clock signals from the input clock signal using the digital information after a predetermined delay time elapses. The output clock signals each have a duty cycle of 50%. The DLL includes: a time-to-digital converter for converting one period (T) of the input clock signal into a digital signal to generate coarse cycle information signals and fine cycle information signals; a first cycle delay unit for generating a first cycle clock signal delayed by T/2 from an internal clock signal and half cycle information signals in response to the coarse cycle information signals and the fine cycle information signals; a second cycle delay unit for generating a second cycle clock signal delayed by T/4 from the input clock signal in response to the coarse cycle information signals and half cycle information signals; and a clock recovery unit for generating the output clock signals in response to the first and second cycle clock signals.

REFERENCES:
patent: 5999027 (1999-12-01), Yamazaki
patent: 6429693 (2002-08-01), Staszewski et al.
patent: 6593773 (2003-07-01), Staszewski et al.
patent: 6731667 (2004-05-01), Lee et al.
patent: 6754613 (2004-06-01), Tabatabaei et al.
patent: 6993109 (2006-01-01), Lee et al.
patent: 2002-101083 (2002-04-01), None
patent: 2000-0075411 (2000-12-01), None

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