Delay locked loop DLL in semiconductor device

Details Delay locked loop DLL in semiconductor device Delay locked loop DLL in semiconductor device

2002-12-31

2004-02-17

Ton, My-Trang Nu (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S161000

Reexamination Certificate

active

06693474

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor device; and, more particularly, to a delay locked loop (DLL) in the semiconductor device.
DESCRIPTION OF RELATED ART
A delay locked loop (DLL) is a kind of a clock compensation circuit for accurately synchronizing a phase of an internal clock signal with that of an external clock signal and is universally applied to memories or ICs, such as SDRAM, DDR SDRAM and the like.
Generally, a chip for a synchronous semiconductor memory device employs a buffer for receiving an external clock signal supplied from an external circuit and generating an internal clock signal necessary to the chip in order to perform a high-speedy operation. A phase difference between the internal clock signal and the external clock signal is generated by passing through internal circuits in the chip. Therefore, operations of the internal circuits are delayed as much as the phase difference. The DLL generates the internal clock signal having the same phase with the external clock signal.
Hereinafter, a conventional DLL will be described according to accompanying drawings.
FIG. 1
is a block diagram illustrating the conventional DLL. The DLL includes a clock buffer
100
, a variable delay line
102
, a clock divider
104
, a delay model
106
, a delay control block
108
, a clock driver
110
and an output terminal
112
. The clock buffer
100
receives and buffers an external clock signal. An output signal from the clock buffer
100
is inputted to the variable delay line
102
. An output signal from the variable delay line
102
is inputted to the clock driver
110
and the output terminal
112
outputs a data signal synchronized with an output signal from the clock driver
110
. The delay model
106
monitors delay time for an output signal from the variable delay line
102
. The clock divider
104
divides the output signal from the clock buffer
100
and the divide signal is inputted to the delay control block
108
. The delay control block
108
compares the divided clock signal outputted from the clock divider
104
and the output signal of the delay model
106
and controls the variable delay line
102
according to a comparison result.
Generally, the delay model
106
is designed by modeling delay time of a delay path for the clock buffer
100
, the clock driver
110
and the output terminal
112
.
The output signal of the delay model
106
and the output signal of the clock divider
104
are inputted to the delay control block
108
for controlling to the variable delay line
102
. The output signal of the variable delay line
102
, which is controlled by the delay control block
108
, is inputted to the clock driver
110
. Finally, the data synchronized with the output signal of the clock driver
110
is outputted from the output terminal
112
.
Since the delay model
106
is designed by modeling delay time for input/output drivers, an I/O voltage, which is used in the input/output drivers, should be used to the delay model
106
for an accurate modeling operation.
Since the I/O voltage has a characteristic that voltage level variation is severe, it is difficult to use the I/O power voltage as a power voltage for the delay model. Therefore, a core voltage Vcore, which is the same voltage level with the I/O voltage and has a stable voltage level, is employed.
If there is not the core voltage Vcore having the same voltage level with the I/O voltage, the I/O voltage has to be used. Recently, as the voltage level used in external semiconductor devices, such as a CPU and the like, interfacing with the memory device is decreased, the voltage level of the I/O voltage may be decreased lower than that of the core voltage Vcore.
Accordingly, if there is no the core voltage Vcore having the same voltage level with that of the I/O voltage, the I/O voltage has to be used, so that the I/O voltage applied to the delay model
14
becomes unstable due to a noise generated in an I/O driver operation. Therefore, there is a problem that a jitter of the DLL is generated.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a delay locked loop (DLL) improving a noise characteristic of a delay model in a semiconductor device.
In accordance with an aspect of the present invention, there is provided a semiconductor device, having a DLL circuit for generating an internal clock signal by receiving an external clock signal, wherein the DLL circuit includes: a delay model for modeling delay time of an intern clock signal delayed from an external clock signal; and a power supply for adjusting a core voltage by an input output voltage and supplying the adjusted voltage to the delay model


REFERENCES:
patent: 5771264 (1998-06-01), Lane
patent: 6314052 (2001-11-01), Foss et al.
patent: 6333896 (2001-12-01), Lee
patent: 6385129 (2002-05-01), Silvestri
patent: 6446180 (2002-09-01), Li et al.
patent: 6549041 (2003-04-01), Waldrop
patent: 6605969 (2003-08-01), Mikhalev et al.

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