Delay locked loop (DLL) based clock synthesis

Details Delay locked loop (DLL) based clock synthesis Delay locked loop (DLL) based clock synthesis

1998-05-18

2000-03-14

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

327166, 327291, H03B 1900

Patent

active

060378123

ABSTRACT:
In a delay locked loop (DLL) based clock signal synthesizer, which overcomes the accumulated jitter and reference clock noise problems of VCO based circuits, the VCO is replaced by a multi-stage delay line formed by differential variable delay elements. The outputs of the delay stages are fed into differential XOR gates. The outputs from the differential XOR gates are fed into a multi-input differential NOR gate. Both the reference clock and delay line output are the inputs to a phase comparator contained in a DLL loop logic block which converts the differential inputs to single ended and uses a digital loop to provide proportional control to correct any detected phase error. The output of the digital loop logic is a vector used to control a current digital-to-analog converter, which is used to mirror a control current to the delay stages of the delay line. The amount of mirrored current controls the delay of the delay stages. The frequency multiplication factor of the clock generating circuit may be adjusted by changing the number of delay elements in the delay chain formed. The period of the synthesized clock signal will be proportional to the number of delay elements.

REFERENCES:
patent: 5786715 (1998-07-01), Halepete
patent: 5838178 (1998-11-01), Marbot

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