Delay locked loop device of the semiconductor circuit

Details Delay locked loop device of the semiconductor circuit Delay locked loop device of the semiconductor circuit

1998-11-20

2000-11-28

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327157, 327284, 331 25, 375373, H03L 700

Patent

active

061540730

ABSTRACT:
Delay Locked Loop device generates an internal clock by receiving an external clock. Multiplexer is provided to receive N delay signals outputted from the first to Nth delay elements which receives the external clock. The Delay Locked Loop device generates the internal clock by selecting one of the N delay signals. The phase of the internal clock follows the phase of the external clock.

REFERENCES:
patent: 4704574 (1987-11-01), Nossen
patent: 5295164 (1994-03-01), Yamamura
patent: 5345119 (1994-09-01), Khoury
patent: 5771264 (1998-06-01), Lane
patent: 5854797 (1998-12-01), Schwartz et al.
patent: 5963069 (1999-10-01), Jefferson et al.

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