Delay-locked loop control

Details Delay-locked loop control Delay-locked loop control

2007-10-09

2010-10-12

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S161000, C375S238000

Reexamination Certificate

active

07812655

ABSTRACT:
This invention relates to devices, a chip, a method and a computer-readable medium for controlling operation of a delay-locked loop. A delay-locked loop unit is adapted to trigger generation of first-type edges of a target signal. A main control unit is adapted to control operation of the delay-locked loop unit in a way that the delay-locked loop unit is turned on before generation of each first-type edge of the target signal and turned off after generation of each first-type edge.

REFERENCES:
patent: 5925133 (1999-07-01), Buxton et al.
patent: 6738675 (2004-05-01), Dai
patent: 6809990 (2004-10-01), Thomann et al.
patent: 7439787 (2008-10-01), Hashim et al.
patent: 7627032 (2009-12-01), O'Malley et al.
patent: 7667625 (2010-02-01), Prodic et al.
patent: 2006/0214712 (2006-09-01), O'Malley et al.
Yousefzadeh, V.; Takayama, T.; Maksimovi, D., “Hybrid DPWM with Digital Delay-Locked Loop,” Computers in Power Electronics, 2006. COMPEL '06. IEEE Workshops on , vol., No., pp. 142-148, Jul. 16-19, 2006.
A. Syed, et al; “Digital Pulse Width Modulator Architectures;” IEEE; 2004 359thAnnual IEEE Power Electronics Specialists Conference; Germany 2004; pp. 4689-4695.
You-Jen Wang, et al; “All-Digital Delay-Locked Loop/Pulsewidth-Control Loop With Adjustable Duty Cycles;” IEEE Journal of Solid-State Circuits, vol. 41, No. 6, Jun. 2006; pp. 1262-1274.
D. Santos, et al; “A CMOS Delay Locked Loop and Sub-Nanosecond Time-to-Digital Converter Chip;” IEEE Transactions on Nuclear Science, vol. 43, No. 3, Jun. 1996; pp. 1717-1719.
R. Aguiar, et al; “Oscilatorless Clock Multiplication”; IEEE International Symposium on Circuits and System, Sydney, Australia, May 2001; whole document.
S. Huerta, et al; “FPGA based Digital Pulse Width Modulator with Time Resolution under 2ns;” IEEE Twenty Second Annual Applied Power Electronics Conference; Anaheim, CA, Feb. 25, 2007-Mar. 1, 2007; whole document.

Affiliated with

Also associated with

Rating

Delay-locked loop control does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Delay-locked loop control, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Delay-locked loop control will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4212880