Delay locked loop circuits and methods preventing erroneous...

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

Reexamination Certificate

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C331S025000, C375S376000

Reexamination Certificate

active

07034590

ABSTRACT:
Delayed locked loop (DLL) circuits and methods using a coarse-fine lock structure which prevent malfunction due to jitter or noise that causes erroneous transitions from a coarse-lock to a fine-lock delay. A phase detector uses two feedback signals to detect a phase of an external clock signal (or reference signal) based on a phase difference between the two feedback signals, thereby enabling a more accurate determination as to when to transition from a coarse-lock to a fine-lock delay. The phase difference of the two feedback signals can be regulated by using frequency information to set a phase difference between the first and second feedback signals to renders the detection process more robust against noise or jitter over a wide frequency band from a low frequency to a high frequency, for determining when to transition from the coarse-lock to the fine-lock.

REFERENCES:
patent: 5744991 (1998-04-01), Jefferson et al.
patent: 6346837 (2002-02-01), Shibayama
patent: 6388485 (2002-05-01), Kim
patent: 6518807 (2003-02-01), Cho
patent: 6765976 (2004-07-01), Oh

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