Delay-locked loop circuits

Details Delay-locked loop circuits Delay-locked loop circuits

2007-11-13

2007-11-13

Nguyen, Linh My (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S155000, C327S156000, C327S159000, C327S161000, C327S162000, C327S163000

Reexamination Certificate

active

11406323

ABSTRACT:
A delay-locked loop (DLL) circuit comprises a voltage controlled delay line (VCDL) including a plurality of identical delay stages connected in series, and a feedback loop including a phase comparator for controlling the VCDL such that the total delay over a number of stages matches the period of the periodic reference signal. Signal outputs are connected to derive their respective output signals from respective nodes within the delay line. The phase comparator compares the phase of first and second differently delayed versions of the reference signal from respective nodes within the variable delay line separated only by a plurality of identical delay stages.

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Takanori Saeki et al: “A 1.3-Cycle Lock Time, Non-PLL/DLL Clock Multiplier Based on Direct Clock Cycle Intepolation for “Clock on Demand””, IEEE Journal of Solid State Circuits, vol. 35, No. 11 (Nov. 2000). 1581-1590.
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