Delay locked loop circuit with improved jitter performance

Details Delay locked loop circuit with improved jitter performance Delay locked loop circuit with improved jitter performance

2002-12-10

2004-07-13

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S161000, C327S149000

Reexamination Certificate

active

06762633

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a delay locked loop circuit with an improved jitter performance, and more particularly to a delay locked loop circuit using a phase mixer for improved jitter performance by using a phase mixer. The delay locked loop circuit according to the present invention can be applicable to a semiconductor memory device and more particularly to all semiconductor devices and computer systems requiring a delay locked loop circuit.
2. Description of the Prior Art
As generally known in the art, the delay locked loop (hereinafter referred to “DLL”) circuit is a clock generating device for compensating skew between an external clock and data, or an external clock and an internal clock.
FIG. 1
is a block diagram illustrating an example of a conventional DLL circuit. An input buffer
101
in the conventional DLL circuit
100
receives and converts an external clock signal exCLK or a reference clock signal into an internal clock signal inCLK having a signal level suitable for an internal circuit. An variable delay circuit
103
receives the clock inCLK from the input buffer
101
and generates an output clock signal dIICLK by delaying for a predetermined time. A main phase determining circuit
105
receives the output clock signal dIICLK and the external clock signal exCLK and detects a phase difference between the two clock signals so that it generates a phase push signal PUSH when a phase of the output clock signal exCLK runs ahead of the phase of the external clock signal exCLK. In constrast, it generates a phase pull signal PULL when the phase of the output clock signal dIICLK lags behind the phase of the external clock signal. Although the main phase determining circuit
105
detects a phase difference between the output clock signal dIICLK and the external clock signal exCLK and generates the phase pull signal PULL or the phase push signal PUSH, since the circuit
100
in
FIG. 1
is for arranging the output clock signal dIICLK and the external clock signal exCLK, there are possibilities for a plurality of variants of the main phase determining circuit
105
such as a circuit to use the internal clock signal inCLK and the output clock signal dIICLK as an input. A delay control circuit
107
receives the phase push signal PUSH or the phase pull signal PULL from the main phase determining circuit
105
, generates a control signal CTRL for controlling a delayed amount of a variable delay line
104
, and supplies the control signal CTRL to the variable delay circuit
103
.
The DLL circuit
100
depicted in
FIG. 1
, as described above, corresponds to a case for obtaining an output clock signal dIICLK having a phase identical to the phase of the external clock signal exCLK. This can be achieved by properly adjusting the amount of the delay of the variable delay circuit
103
. The main phase determining circuit
105
determines that the phase of the output clock signal dIICLK is slow by comparing the phases between the external clock signal exCLK ad the output clock signal dIICLK and activates the phase push signal PUSH. If the phase push signal PUSH is provided to the delay control circuit
107
, the delay control circuit
107
generates the control signal CTRL which reflects the phase push signal PUSH, so that the amount of delay in the variable delay circuit
103
is slightly increased. The amount of the delay is increased little by little so that the phase of the output clock signal dIICLK will approach the phase of the external clock signal exCLK. In contrast, if the phase of the output clock signal dIICLK lags the phase of the external clock signal exCLK, the main phase determining circuit
105
activates the phase pull signal which results in the decrease of the amount of delay in the variable delay circuit
103
through the delay control circuit
107
. Through the procedures described as above, the phase of the output clock signal dIICLK is adapted to the phase of the external clock signal exCLK. Under such conditions, the phase of the output clock signal dIICLK swings about the phase of the external clock signal exCLK at least by minimum variable delay amount (hereinafter referred to unit delay) to be increased or decreased by the phase push signal PUSH or the phase pull signal PULL.
The DLL has a variety of performance indices, one of the indices being jitter performance. The jitter means a swing amount as the phase of the DLL output signal reciprocates minutely. The less the amount of the jitter is, the superior the DLL is. Errors in the phase determining circuit and the unit delay of the variable delay line are restricted to factors affecting the jitter performance. Until now, the error and the unit delay have been used to enhance jitter performance by mainly improving each value thereof.
FIG. 2
shows the jitter performance of the circuit in FIG.
1
. When the phase of the reference signal is set to 0 (zero), the main phase determining circuit
105
should swing the phase of the output signal of the delay locked loop circuit
100
in
FIG. 1
by at least the amount of error. When a maximum error of the main phase determining circuit
105
is set to &Dgr;
PD
, a jitter window, an error area due to the main phase determining circuit
105
, is represented in the equation
1
, and corresponds to portions indicated by &PHgr;P in
FIGS. 2A and 2B
.
|
JW
|<&Dgr;
PD
  [Equation 1]
where the jitter is increased by the unit delay t
UD
, it gets decreased due to the signals PUSH and PULL. When the jitter is increased toward the right side by the unit delay t
UD
due to the signal PUSH, as illustrated in
FIG. 2A
, the jitter window at that time is represented as equation 2. Meanwhile, as illustrated in
FIG. 2B
, when the jitter is increased toward the left side by the unit delay t
UD
due to the signal PULL, the jitter window thereof is represented as equation 3. Therefore, the jitter window becomes sum of the equations 2 and 3 finally and is expressed by equation 4. A maximum phase error &PHgr;
MAX
is expressed by the equation 5.
−&Dgr;
PD
<JW
a1
<&Dgr;
PD
+t
UD
  [Equation 2]
−&Dgr;
PD
−t
UD
<JW
b1
<&Dgr;
PD
  [Equation 3]
|
JW
f1
|<&Dgr;
PD
+t
UD
  [Equation 4]
|&PHgr;
MAX1
|=&Dgr;
PD
+t
UD
  [Equation 5]
It can be understood that the jitter and the maximum phase error can be reduced by decreasing the &Dgr;
Pd
and t
UD
, and also can be enhanced by other ways as shown in of
FIGS. 2A and 2B
. In other words, since, as shown in
FIGS. 2A and 2B
, the jitter windows are divergent from each other, the jitters can be reduced by as much as the amount in which two jitter windows overlap.
FIG. 3
shows a block diagram of a conventional delay locked loop circuit for improving the jitter performance by using the facts. The main phase determining circuit
300
, as shown in
FIG. 3
, includes two phase determining circuits
301
and
303
, and a delay component
305
as essential components. Other characteristics are that the clock signal provided to an input signal terminal of the second phase determining circuit
303
passes through the delay component
305
. In the description hereinafter, it is assumed that logic values of the signal PUSH or PULL become a logic high when the logic values are activated, and become a logic low when the values are not activated. Moreover, both of the signals PUSH and PULL, the outputs of one phase determining circuit cannot be logic high simultaneously. Only the signals must be determined as the logic high and or the logic low.
As shown in
FIG. 3
, the reference clock signal REF is directly provided to reference signal terminals REF of two phase determining circuits
301
and
303
. Though an input signal IN is directly provided to an input signal terminal IN of the first phase determining circuit
301
, a signal delayed as much as to is provided to an input signal terminal IN o

Affiliated with

Also associated with

Rating

Delay locked loop circuit with improved jitter performance does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Delay locked loop circuit with improved jitter performance, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Delay locked loop circuit with improved jitter performance will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3245612