Delay locked loop circuit for semiconductor memory apparatus

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Rectangular or pulse waveform width control

Reexamination Certificate

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C327S156000, C327S293000

Reexamination Certificate

active

07548101

ABSTRACT:
A delay locked loop circuit for a semiconductor memory apparatus includes a duty cycle correcting part that corrects and outputs duty cycles of internal clocks. A clock pulse width detecting part detects a pulse width of an external clock and outputs a pulse width detecting signal. A driving part divides a phase of the output of the duty cycle correcting part, adjusts a pulse width of at least one of two signals, which are obtained by dividing the phase, in accordance with the pulse width detecting signal, and outputs the two signals as delay locked loop clocks.

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patent: 6798248 (2004-09-01), Hazucha et al.
patent: 6813197 (2004-11-01), Park
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patent: 7154311 (2006-12-01), Lim
patent: 7170313 (2007-01-01), Shin
patent: 2006/0267649 (2006-11-01), Park et al.
patent: 2005251370 (2005-09-01), None
patent: 1020040091975 (2004-11-01), None
patent: 1020040095965 (2004-11-01), None

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