Delay locked loop circuit, digital predistortion type...

Details Delay locked loop circuit, digital predistortion type... Delay locked loop circuit, digital predistortion type...

2005-01-07

2009-06-30

Payne, David C (Department: 2611)

Pulse or digital communications

Transmitters

Antinoise or distortion

C455S114300

Reexamination Certificate

active

07555058

ABSTRACT:
Disclosed are a delay locked loop circuit capable of accurately extracting nonlinear distortion superimposed on an output of a digital predistortion type transmitter, the digital predistortion type transmitter, and a wireless base station using the same. The delay locked loop circuit outputting a smoothed signal to the variable delay element, in which delay control is implemented for checking distortion occurring to the output IQ signals due to the same passing through the analog circuit by means of the variable delay element. Either the first input IQ signals or the second input IQ signals are signals generated as a result of output IQ signals Io, Qo undergoing digital-to-analog conversion, and again undergoing analog-to-digital conversion after passing through an analog circuit. In particular, an IIR filter may be used for the variable delay element.

REFERENCES:
patent: 6570444 (2003-05-01), Wright
patent: 6836517 (2004-12-01), Nagatani et al.
patent: 7106133 (2006-09-01), Hamada et al.
patent: 2003/0231716 (2003-12-01), Unger
patent: 2001-189685 (2001-07-01), None
patent: 2003-174332 (2003-06-01), None
patent: 2003-273663 (2003-09-01), None

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