Delay locked loop circuit capable of operating in a low...

Details Delay locked loop circuit capable of operating in a low... Delay locked loop circuit capable of operating in a low...

2006-03-21

2006-03-21

Nguyen, Minh (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C375S376000

Reexamination Certificate

active

07015737

ABSTRACT:
A delay-locked loop circuit may include a frequency doubler for increasing a frequency of a clock signal and a frequency divider for decreasing the frequency of the clock signal. The delay-locked loop circuit can be selectively operated in a low frequency and a high frequency by the frequency doubler and the frequency divider.

REFERENCES:
patent: 5955902 (1999-09-01), Takada et al.
patent: 5970110 (1999-10-01), Li
patent: 6208183 (2001-03-01), Li et al.
patent: 6501312 (2002-12-01), Nguyen
patent: 6906566 (2005-06-01), Drexler

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