Delay locked loop circuit and signal delay locking method

Details Delay locked loop circuit and signal delay locking method Delay locked loop circuit and signal delay locking method

2007-08-28

2007-08-28

Cox, Cassandra (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S149000

Reexamination Certificate

active

11307803

ABSTRACT:
A delay locked loop circuit and signal delay locking method are provided. First, the start-up circuit minimizes the delay time between an output signal and a reference signal during an initial period. Secondly, the phase correction circuit increases the delay time during an correction period. The present invention ensures that the phase difference between the output signal and the reference signal is correctly detected by the delay locked loop circuit, so that harmonic lock and phase ambiguity can be avoided.

REFERENCES:
patent: 5297181 (1994-03-01), Barr et al.
patent: 5663665 (1997-09-01), Wang et al.
patent: 6624674 (2003-09-01), Zhao
patent: 6667643 (2003-12-01), Ko
patent: 7116178 (2006-10-01), Abel
patent: 2003/0206066 (2003-11-01), Harwood
patent: 2004/0208271 (2004-10-01), Gruenberg et al.

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