Delay-locked loop circuit and method using a ring oscillator...

Details Delay-locked loop circuit and method using a ring oscillator... Delay-locked loop circuit and method using a ring oscillator...

2001-11-19

2004-07-06

Mis, David C. (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural a.f.s. for a single oscillator

C331S00100A, C331S017000, C331S045000, C331S057000, C327S156000, C327S158000, C327S159000

Reexamination Certificate

active

06759911

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to integrated circuits, and more specifically to synchronizing an external clock signal applied to an integrated circuit with internal clock signals generated in the integrated circuit in response to the external clock signal.
BACKGROUND OF THE INVENTION
In synchronous integrated circuits, the integrated circuit is clocked by an external clock signal and performs operations at predetermined times relative the rising and falling edges of the applied clock signal. Examples of synchronous integrated circuits include synchronous memory devices such as synchronous dynamic random access memories (SDRAMs), synchronous static random access memories (SSRAMs), and packetized memories like SLDRAMs and RDRAMs, and include other types of integrated circuits as well, such as microprocessors. The timing of signals external to a synchronous memory device is determined by the external clock signal, and operations within the memory device typically must be synchronized to external operations. For example, commands are placed on a command bus of the memory device in synchronism with the external clock signal, and the memory device must latch these commands at the proper times to successfully capture the commands. To latch the applied commands, an internal clock signal is developed in response to the external clock signal, and is typically applied to latches contained in the memory device to thereby clock the commands into the latches. The internal clock signal and external clock must be synchronized to ensure the internal clock signal clocks the latches at the proper times to successfully capture the commands. In the present description, “external” is used to refer to signals and operations outside of the memory device, and “internal” to refer to signals and operations within the memory device. Moreover, although the present description is directed to synchronous memory devices, the principles described herein are equally applicable to other types of synchronous integrated circuits.
Internal circuitry in the memory device that generates the internal clock signal necessarily introduces some time delay, causing the internal clock signal to be phase shifted relative to the external clock signal. As long as the phase-shift is minimal, timing within the memory device can be easily synchronized to the external timing. To increase the rate at which commands can be applied and at which data can be transferred to and from the memory device, the frequency of the external clock signal is increased, and in modern synchronous memories the frequency is in excess of 100 MHZ. As the frequency of the external clock signal increases, however, the time delay introduced by the internal circuitry becomes more significant. This is true because as the frequency of the external clock signal increases, the period of the signal decreases and thus even small delays introduced by the internal circuitry correspond to significant phase shifts between the internal and external clock signals. As a result, the commands applied to the memory device may no longer be valid by the time the internal clock signal clocks the latches.
To synchronize external and internal clock signals in modern synchronous memory devices, a number of different approaches have been considered and utilized, including delay-locked loops (DLLs), phased-locked loops (PLLs), and synchronous mirror delays (SMDs), as will be appreciated by those skilled in the art. As used herein, the term synchronized includes signals that are coincident and signals that have a desired delay relative to one another.
FIG. 1
is a functional block diagram illustrating a conventional delay-locked loop
100
including a variable delay line
102
that receives a clock buffer signal CLKBUF and generates a delayed clock signal CLKDEL in response to the clock buffer signal. The variable delay line
102
controls a variable delay VD of the CLKDEL signal relative to the CLKBUF signal in response to a delay adjustment signal DADJ. A feedback delay line
104
generates a feedback clock signal CLKFB in response to the CLKDEL signal, the feedback clock signal having a model delay D
1
+D
2
relative to the CLKDEL signal. The D
1
component of the model delay D
1
+D
2
corresponds to a delay introduced by an input buffer
106
that generates the CLKBUF signal in response to an external clock signal CLK, while the D
2
component of the model delay corresponds to a delay introduced by an output buffer
108
that generates a synchronized clock signal CLKSYNC in response to the CLKDEL signal. Although the input buffer
106
and output buffer
108
are illustrated as single components, each represents all components and the associated delay between the input and output of the delay-locked loop
100
. The input buffer
106
thus represents the delay D
1
of all components between an input that receives the CLK signal and the input to the variable delay line
102
, and the output buffer
108
represents the delay D
2
of all components between the output of the variable delay line and an output at which the CLKSYNC signal is developed.
The delay-locked loop
100
further includes a phase detector
110
that receives the CLKFB and CLKBUF signals and generates a delay control signal DCONT having a value indicating the phase difference between the CLKBUF and CLKFB signals. One implementation of a phase detector is described in U.S. Pat. No. 5,946,244 to Manning (Manning), which is assigned to the assignee of the present patent application and which is incorporated herein by reference. A delay controller
112
generates the DADJ signal in response to the DCONT signal from the phase detector
110
, and applies the DADJ signal to the variable delay line
102
to adjust the variable delay VD. The phase detector
110
and delay controller
112
operate in combination to adjust the variable delay VD of the variable delay line
102
as a function of the detected phase between the CLKBUF and CLKFB signals.
In operation, the phase detector
110
detects the phase difference between the CLKBUF and CLKFB signals, and the phase detector and delay controller
112
operate in combination to adjust the variable delay VD of the CLKDEL signal until the phase difference between the CLKBUF and CLKFB signals is approximately zero. More specifically, as the variable delay VD of the CLKDEL signal is adjusted the phase of the CLKFB signal from the feedback delay line
104
is adjusted accordingly until the CLKFB signal has approximately the same phase as the CLKBUF signal. When the delay-locked loop
100
has adjusted the variable delay VD to a value causing the phase shift between the CLKBUF and CLKFB signals to equal approximately zero, the delay-locked loop is said to be “locked.” When the delay-locked loop
100
is locked, the CLK and CLKSYNC signals are synchronized. This is true because when the phase shift between the CLKBUF and CLKFB signals is approximately zero (i.e., the delay-locked loop
100
is locked), the variable delay VD has a value of NTCK−(D
1
+D
2
) as indicated in
FIG. 1
, where N is an integer and TCK is the period of the CLK signal. When VD equals NTCK−(D
1
+D
2
), the total delay of the CLK signal through the input buffer
106
, variable delay line
102
, and output buffer
108
is D
1
+NTCK−(D
1
+D
2
)+D
2
, which equals NTCK. Thus, the CLKSYNC signal is delayed by NTCK relative to the CLK signal and the two signals are synchronized since the delay is an integer multiple of the period of the CLK signal. Referring back to the discussion of synchronous memory devices above, the CLK signal corresponds to the external clock signal and the CLKDEL signal corresponds to the internal clock signal.
FIG. 2
is a signal timing diagram illustrating various signals generated during operation of the delay-locked loop
100
of FIG.
1
. In response to a rising-edge of the CLK signal at a time T
0
, the CLKBUF signal goes high the delay D
1
later at a time T
1
. Initially, the variable delay VD as a val

Affiliated with

Also associated with

Rating

Delay-locked loop circuit and method using a ring oscillator... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Delay-locked loop circuit and method using a ring oscillator..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Delay-locked loop circuit and method using a ring oscillator... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3190867