Delay locked loop circuit and method for testing the...

Details Delay locked loop circuit and method for testing the... Delay locked loop circuit and method for testing the...

2006-07-11

2006-07-11

Deb, Anjan (Department: 2858)

Electricity: measuring and testing

Measuring, testing, or sensing electricity, per se

Frequency of cyclic current or voltage

C324S527000

Reexamination Certificate

active

07075285

ABSTRACT:
A delay locked loop (DLL) circuit and method for testing the operability of the circuit utilizes one or more test signal sources and a test signal receiver to selectively transmit test signals, for example, static test signals, through an array of delay elements of the DLL circuit. The resulting output signals of the array are used to determine whether any delay element or a tap selector of the DLL circuit has malfunctioned, e.g., stuck-at fault.

REFERENCES:
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patent: 6115305 (2000-09-01), Pathak et al.
patent: 6437553 (2002-08-01), Maloney et al.
patent: 6486651 (2002-11-01), Lee et al.
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patent: 6815986 (2004-11-01), Roy et al.
patent: 2004/0012420 (2004-01-01), Roy et al.

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