Delay locked loop circuit and control method of the same

Details Delay locked loop circuit and control method of the same Delay locked loop circuit and control method of the same

2011-04-12

2011-04-12

Cox, Cassandra (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S149000

Reexamination Certificate

active

07924075

ABSTRACT:
A delay locked loop capable of preventing delay locking time from being increased, even if the operational environment fluctuates. The delay locked loop circuit includes a delay line for delaying and outputting a reference clock signal, a phase detection unit for detecting a phase difference between the reference clock signal and an output signal of the delay line and then outputting a phase detection signal and a first delay mode decision signal, a control unit for outputting a delay control signal to control the delay line according to the phase detection signal and a second delay mode decision signal, and an error decision unit for detecting an error of the first delay mode decision signal according to the delay control signal and the output signal of the delay line and outputting the second delay mode decision signal according to a result of the error detection.

REFERENCES:
patent: 2003/0030473 (2003-02-01), Lee
patent: 2005/0052252 (2005-03-01), Galibois
patent: 2005/0127963 (2005-06-01), Johnson
patent: 2005/0132087 (2005-06-01), Glinski et al.
patent: 2000059183 (2000-02-01), None
patent: 1020050001152 (2005-01-01), None
patent: 1020070110627 (2007-11-01), None

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