Delay-locked loop circuit

Details Delay-locked loop circuit Delay-locked loop circuit

2008-05-27

2008-05-27

Cox, Cassandra (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S149000

Reexamination Certificate

active

11394389

ABSTRACT:
The delay of delay circuit10is set within a predetermined range, and, in a stop mode, the clock pulses of 1 cycle of clock signal φin when transition is made from the stop mode to the DLL mode are excluded from the object detected by phase detector20such that phase difference Δφ′ detected by phase detector20is within a prescribed range when said transition is performed. As a result, it is possible to lock the delay of clock signal φdin with respect to clock signal φin at a desired value (e.g., “2π”), and it is possible to prevent locking to an undesired abnormal state.

REFERENCES:
patent: 6803797 (2004-10-01), Park

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