Delay locked loop circuit

Details Delay locked loop circuit Delay locked loop circuit

2007-11-20

2007-11-20

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S149000

Reexamination Certificate

active

10965985

ABSTRACT:
The DLL circuit detects a frequency of an external clock signal and adjusts a coarse delay during a DLL circuit operation, thereby quickly terminating a feedback operation of the DLL circuit and having a reduced circuit area of a delay line. Therefore, the DLL circuit can be used for next generation high-integration and high-frequency memory devices such as DDR2 SDRAMs.

REFERENCES:
patent: 6066969 (2000-05-01), Kawasaki et al.
patent: 6342796 (2002-01-01), Jung
patent: 6437619 (2002-08-01), Okuda et al.
patent: 6492852 (2002-12-01), Fiscus
patent: 6509776 (2003-01-01), Kobayashi et al.

Affiliated with

Also associated with

Rating

Delay locked loop circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Delay locked loop circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Delay locked loop circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3833990