Delay-locked loop circuit

Details Delay-locked loop circuit Delay-locked loop circuit

2000-10-17

2002-07-02

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S149000, C327S158000, C327S161000, C327S276000

Reexamination Certificate

active

06414526

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to electronics, and, more particularly a delay-locked loop circuit (DLL).
BACKGROUND OF THE INVENTION
A delay-locked loop (DLL) is a circuit with feedback which, on the basis of a periodic input signal of period T, can output a periodic signal with the same period T and with a delay &Dgr;t relative to the input signal equal to and locked to the period T of the input signal.
Known DLLs include a delay line wherein the delay can be varied in a controlled manner. The delay line receives the periodic signal of period T as an input and produces the periodic signal delayed by &Dgr;t as an output. The periodic input signal and the delayed periodic signal are supplied to a phase comparator circuit. On the basis of the phase difference detected between the delayed periodic signal and the periodic input signal, the phase comparator controls delay-line control logic circuitry which acts on the delay line to bring about an increase or a decrease in the delay &Dgr;t to keep the delay equal to the period T.
The delay line is normally formed by a plurality of N elemental delay units which are normally identical to one another, at least theoretically, and each of which can introduce an elemental delay equal to &Dgr;t/N. In the locked condition, i.e., &Dgr;t=T, the DLL can thus supply, on the basis of the periodic input signal, N periodic signals all of equal period and each delayed relative to the preceding signal by a time T/N.
DLL circuits have various applications. In particular, these circuits may be used in the synchronous digital communications field, in which it is essential to have synchronization circuits to correctly decode data travelling on the communication channels. Reference is directed to European patent application No. 99830518.9 filed Aug. 6, 1999, the entirety of which is incorporated herein by reference and is assigned to the assignee of the present invention. A DLL is disclosed in the European patent application in which a synchronous digital hierarchy (SDH) communication interface, as an alternative to the usual phase-locked loop (PLL) circuits, is used for synchronization with a received data flow.
However, a disadvantage of known DLLs is that the locked condition may not occur, as would be desirable, with a delay &Dgr;t=T, but may occur instead with delays which are multiples or submultiples of the period T of the input signal. This is due basically to the fact that conventional phase comparators used in known DLLs cannot detect the phase difference correctly outside the range +/−&pgr; rad.
For a better understanding of the reason for the above statement, reference is made to
FIG. 1
in which the periodic input signal is indicated as CKin and the output signal of the DLL, i.e., the output signal of the delay line, is indicated as Ckout. The output signal has a delay locked to the period of the input signal. The phase comparator operates on the leading edge RE of the input signal CKin and of the output signal CKout. In case a) of
FIG. 1
, the output signal CKout has a delay &Dgr;t
1
relative to the input signal Ckin, where t/2<&Dgr;t
1
<T. The phase comparator detects the phase advance of the signal CKout relative to the signal CKin and communicates it to the control logic circuitry which modifies the delay &Dgr;t of the delay line so as to increase the delay.
In case b), the output signal CKout has a delay &Dgr;t
2
relative to the input signal Ckin, where T<&Dgr;t
2
<(3/2)T. The phase comparator detects the phase delay of the output signal CKout relative to the signal CKin and communicates it to the control logic circuitry which modifies the delay &Dgr;t of the delay line so as to reduce the delay. In cases a) and b), the DLL can lock onto the period T of the input signal.
Case c) will now be examined. The output signal CKout has a delay &Dgr;t
3
relative to the input signal Ckin, where &Dgr;t
3
>(3/2)T. In order for the DLL to be locked, the delay introduced by the delay line would have to be decreased. However, the phase comparator interprets this delay as an advance and informs the control logic circuitry of the need to increase the delay of the line. This is going in the opposite direction to that required to achieve locking.
Similarly, in case d) the output signal CKout has a delay &Dgr;t
4
relative to the input signal Ckin, where &Dgr;t
4
<T/2. For the DLL to lock, it would therefore be necessary to increase the delay introduced by the line. However, the phase comparator interprets this advance as an excessive delay and informs the control logic circuitry to reduce the delay of the line. Again, this is going in the opposite direction to that required to achieve locking.
In the two cases c) and d), the delay locked loop does not tend towards the locking condition, but tends away from this condition. This occurs until, in case c), the maximum value of the delay which can be introduced by the line is reached and, in case d), the minimum value of the delay is reached. That is, until the delay locked loop reaches the limit of its own dynamic range, and the feedback loop can no longer operate.
SUMMARY OF THE INVENTION
In view of the prior art described above, an object of the present invention is to provide an improved DLL which is not affected by the disadvantages of conventional DLL circuits.
According to the present invention, this object is achieved by a delay-locked loop (DLL) circuit comprising a delay line with a delay which can be varied in a controlled manner to delay a periodic input signal of period T, and a control circuit for controlling the delay line to lock the delay to the period T.
The delay line supplies to the control circuit a plurality of delayed periodic signals. Each signal is preferably delayed relative to the periodic input signal by a respective fraction of the delay. The control circuit preferably comprise a sequence-detector circuit which can periodically detect, in the delayed periodic signals, characteristic sequences of digital values indicative of the delay. The control circuit can bring about a reduction or an increase in the delay for locking to the period T in dependence on the type of characteristic sequence.


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