Delay locked loop circuit

Details Delay locked loop circuit Delay locked loop circuit

2008-12-30

2010-11-30

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S149000

Reexamination Certificate

active

07843240

ABSTRACT:
A delay locked loop circuit includes a delay locking unit configured to output an internal clock by delaying a reference clock as much as a first delay amount in response to a phase comparison result of comparing a phase of the reference clock with a phase of a feedback clock that is generated based on delay modeling of a semiconductor memory device, and a noise sensor configured to control variation of the first delay amount caused by an external noise to be less than a second delay amount after locking the internal clock.

REFERENCES:
patent: 7253668 (2007-08-01), Johnson
patent: 7375565 (2008-05-01), Kwak
patent: 7414445 (2008-08-01), Heyne
patent: 7605623 (2009-10-01), Yun et al.
patent: 7649389 (2010-01-01), Bae
patent: 2010/0039148 (2010-02-01), Petrie
patent: 2010/0060335 (2010-03-01), Kwak et al.
patent: 1020010065899 (2001-07-01), None
patent: 1020020002565 (2002-01-01), None
patent: 1020030025326 (2003-03-01), None
patent: 1020050013737 (2005-02-01), None
Notice of Preliminary Rejection issued from Korean Intellectual Property Office on Nov. 27, 2009.
Notice of Allowance issued from Korean Intellectual Property Office on Apr. 20, 2010.

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