Delay locked loop circuit

Details Delay locked loop circuit Delay locked loop circuit

2006-06-30

2008-11-11

Cox, Cassandra (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S149000

Reexamination Certificate

active

07449930

ABSTRACT:
A delay locked loop (DLL) circuit for a synchronous dynamic random access memory (SDRAM) is provided. If a locking state is broken due to an external change such as a change of tCK or power supply voltage, indicating that a delay of a delay replication modeling unit involved in a DRAM is abruptly changed, the locking state can be recovered within a certain time, e.g., 200 tCK, by creating an internal reset signal in the DLL circuit by a circuit that monitors the state and then conducting a phase update using a rough delay value.

REFERENCES:
patent: 6049239 (2000-04-01), Eto et al.
patent: 6867627 (2005-03-01), Murtagh
patent: 6989700 (2006-01-01), Kim
patent: 7019573 (2006-03-01), Matsuno
patent: 7026859 (2006-04-01), Yang et al.
patent: 7282974 (2007-10-01), Lee
patent: 2005/0110541 (2005-05-01), Jeon
patent: 2005/0140408 (2005-06-01), Lim
patent: 2005/0195004 (2005-09-01), Kim
patent: 2004-362757 (2004-12-01), None
patent: 2005-251370 (2005-09-01), None
patent: 2003-0016281 (2003-02-01), None

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