Delay locked loop circuit

Details Delay locked loop circuit Delay locked loop circuit

1998-07-08

1999-11-30

Tran, Toan

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327156, H03L 706

Patent

active

059949341

ABSTRACT:
Provided is a DLL circuit that can execute a precise delay synchronization operation without increasing the variable delay time range of a delay line. The DLL circuit comprises a phase comparator (3), a charge pump (6), an LPF (8) and a delay line (9), and operates to match phases of an input signal (CLKIN) and a feedback signal (FBCLK). The phase comparator (3) always outputs a phase comparison result that causes a delay time of the delay line (9) to increase, at the time of initial operation after a reset operation. The LPF (8) outputs a delay adjusting signal (S8) indicating that a delay time due to the delay line (9) becomes the minimum, in executing a reset.

REFERENCES:
patent: 4812783 (1989-03-01), Honjo et al.
patent: 5347232 (1994-09-01), Nishimichi
patent: 5554945 (1996-09-01), Lee et al.
patent: 5896066 (1999-04-01), Katayama et al.
Thomas H. Lee, et al., "A 2.5V CMOS Delay-Locked Loop for an 18 Mbit, 500 Megabyte/s DRAM," IEEE Journal of Solid-State Circuits, vol. 29, No. 12, Dec. 1994, pp. 1491-1496.

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