Delay locked loop capable of preventing false lock and...

Details Delay locked loop capable of preventing false lock and... Delay locked loop capable of preventing false lock and...

2007-01-02

2007-01-02

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S149000, C327S161000

Reexamination Certificate

active

10907027

ABSTRACT:
A DLL capable of preventing false lock includes a false-lock detector, a delay line coupled for using at least one delay lag of the delay line to delay an incoming clock signal and produce at least one delay clock, and a charge pump coupled to the false-lock detector for adjusting a control voltage according to an upward or downward adjustment signal. The false-lock detector includes a first phase detector coupled to a first clock signal and a second clock signal for comparing phases of the first clock signal and the second clock signal to produce a phase difference signal; an average circuit coupled to the first phase detector for generating an average signal corresponding to an average of the phase difference signal; and a comparator circuit coupled to the average circuit for comparing the average signal with at least one reference signal to produce the upward or downward adjustment signal.

REFERENCES:
patent: 5144156 (1992-09-01), Kawasaki
patent: 5940609 (1999-08-01), Harrison
patent: 6330296 (2001-12-01), Atallah et al.
patent: 6452431 (2002-09-01), Waldrop
patent: 6469550 (2002-10-01), Kurd
patent: 6633190 (2003-10-01), Alvandpour et al.
patent: 6667643 (2003-12-01), Ko
patent: 6927635 (2005-08-01), Miki et al.
patent: 6954097 (2005-10-01), Harrison

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