Delay locked loop based clock synthesizer using a dynamically ad

Details Delay locked loop based clock synthesizer using a dynamically ad Delay locked loop based clock synthesizer using a dynamically ad

1993-11-30

1995-10-31

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327261, 327244, 327113, 327269, H03K 5159

Patent

active

054633370

ABSTRACT:
A delay-locked-loop based clock synthesizer for generating, from a reference signal, a clock signal having a frequency different from a frequency of the reference signal includes a delay-locked-loop circuit having a plurality of controllable delay elements serially connected to one another. Each of the delay elements delays the reference signal by an adjustable quantum of time such that the delay elements generate a plurality of delayed signals. A first multiplexer routes one of the delayed signals to a phase detector, which generates a control signal indicative of a difference between a phase of the routed delayed signal and a phase of the reference signal. A feedback loop transfers the control signal from the phase detector to the delay elements, wherein each of the delay elements adjusts, in accordance with the control signal, the quantum of time by which they each delay the reference signal, such that the phase of the reference signal is synchronized with the phase of the routed delayed signal. The clock synthesizer also includes one or more mixing circuits for logically combining the delayed signals such that the mixing circuits generate logically combined signals. A second multiplexer routes one of the received logically combined signals to an output of the second multiplexer, wherein the routed logically combined signal represents the clock signal.

REFERENCES:
patent: 5049766 (1991-09-01), van Driest et al.
patent: 5120990 (1992-06-01), Koker
patent: 5260608 (1993-11-01), Marbot
Floyd M. Gardner, Charge-Pump Phase-Lock Loops, Nov., 1980, pp. 1849-1858.
Jeff Sonntag, Robert Leonowich, Session 11: High-Speed Communication IC's; FAM 11.5: A Monolithic CMOS 10MHz DPLL for Burst-Mode Data Retiming,1900 IEE International Solid-State Circuits Conference (ISSCC 90) Feb. 16, 1990. pp. 194-195.

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