Delay locked loop based circuit for data communication

Details Delay locked loop based circuit for data communication Delay locked loop based circuit for data communication

1999-12-30

2002-10-15

Chin, Stephen (Department: 2734)

Pulse or digital communications

Equalizers

Automatic

C375S350000, C708S313000, C708S316000, C708S322000, C341S141000, C341S142000, C341S159000

Reexamination Certificate

active

06466615

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to equalization of high speed digital communication channels using a threshold multiplexing feedback digital filter.
BACKGROUND
In high speed digital communication systems, communication channels often suffer from intersymbol interference (ISI). In such systems, coherent detection and equalization are necessary to achieve satisfactory performance. Equalizations are typically done using either linear digital filters such as finite impulse response (FIR) filters or non-linear digital filters such as decision feedback equalization (DFE) filters. Equalization can also be done using analog filters before sampling occurs.
Theoretically, FIR filters can be used to approximate any time-invariant impulse response. with a large number of taps. The DFE's, which remove both pre- and post-cursor ISI using a feedforward FIR filter. followed by a feedback infinite impulse response (IIR) filter and a decision non-linearity, are reported to have better equalization results. However, most digital equalizers reported so far are very expensive to implement in very large scale integration (VLSI) systems due to the requirements of large device and silicon area count for high throughput data processing and high speed analog to digital (A/D) conversion. The analog equalizer solutions, on the other hand, can be used to significantly reduce the equalizer device count. However, they suffer from poor design flexibility, reusability, testability, and manufacturability properties of the analog VLSI circuits.
SUMMARY
In accordance with the invention, there is disclosed an apparatus including a plurality of quantizers each configured to compare a selected threshold signal with an input signal and generate an output, a multiplexer, coupled to the plurality of quantizers, that selects one of the plurality of quantizer outputs according to a frequency response, and a multiplication-accumulation (MAC) unit, coupled to the multiplexer, the MAC to generate an output based on a previously selected one of the quantizer outputs according to the frequency response.


REFERENCES:
patent: 5519398 (1996-05-01), Satoh et al.
patent: 5617090 (1997-04-01), Ma et al.
patent: 5768322 (1998-06-01), Nishizawa et al.
patent: 6061396 (2000-05-01), Everitt
patent: 6289062 (2001-09-01), Wang et al.
patent: 6313882 (2001-11-01), Limberg et al.
patent: 6362760 (2002-03-01), Kober et al.

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