Delay locked loop and operating method thereof

Details Delay locked loop and operating method thereof Delay locked loop and operating method thereof

2010-07-02

2010-12-28

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S153000

Reexamination Certificate

active

07859316

ABSTRACT:
A delay locked loop (DLL) includes a delay-locking unit configured to generate first and second delay clocks corresponding to first and second clock edges of a reference clock for achieving a delay-locking; a phase detection unit configured to detect a phase difference between the first and second delay clocks to output a weight selection signal; a weight storage unit configured to store the weight selection signal obtained during a predetermined period from a point of time when the first and second delay clocks are delay locked; and a phase mixing unit configured to mix phases of the first and second delay clocks to output a DLL clock by applying a weight corresponding to the stored weight selection signal in the weight storage unit.

REFERENCES:
patent: 6956418 (2005-10-01), Kwak et al.
patent: 7142026 (2006-11-01), Kwak
patent: 7282974 (2007-10-01), Lee
patent: 7358784 (2008-04-01), Kim et al.
patent: 7428286 (2008-09-01), Kim
patent: 2003/0219088 (2003-11-01), Kwak
patent: 2005/0093600 (2005-05-01), Kwak
patent: 2005/0238128 (2005-10-01), Kim
patent: 2008/0012615 (2008-01-01), Park

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