Delay locked loop and its control method for correcting a...

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

Reexamination Certificate

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C327S175000

Reexamination Certificate

active

07142026

ABSTRACT:
A delay locked loop (DLL) capable of correcting a duty ratio including: a clock buffer for receiving an external clock signal and an inverted external clock signal to generate a rising edge clock signal; a delay unit for delaying the rising edge clock signal based on a first comparison signal in order to generate a first internal clock signal, a second internal clock signal, a first delay locking signal and a second delay locking signal; a duty correction unit for receiving the first and the second internal clock signals and the first and the second delay locking signals to generate a mixed clock signal; a delay model unit for delaying the mixed clock signal to generate a feed-backed clock signal; and a first phase detector for receiving the external clock signal and the feed-backed clock signal to generate the first comparison signal.

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