Delay locked loop and its control method

Details Delay locked loop and its control method Delay locked loop and its control method

2006-05-16

2006-05-16

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S175000

Reexamination Certificate

active

07046059

ABSTRACT:
A delay locked loop (DLL) capable of correcting a duty ratio of a clock signal including: a clock buffer which receives an external clock signal for outputting a rising edge clock signal; a delay unit for delaying the rising edge clock signal based on a first comparison signal in order to generate a first internal clock signal, a second internal clock signal, a first delay locking signal and a second delay locking signal; a duty correction unit for receiving the first and the second internal clock signals and the first and the second delay locking signals and generating a delay locked clock signal by correcting a duty cycle of the external clock signal; and a clock feed-back unit for receiving the delay locked clock signal and the external clock signal in order to generate the first comparison signal.

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