Delay locked loop and clock generation method thereof

Details Delay locked loop and clock generation method thereof Delay locked loop and clock generation method thereof

2007-09-11

2007-09-11

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S161000, C327S175000

Reexamination Certificate

active

10880120

ABSTRACT:
A semiconductor device for correcting a duty of a clock signal includes a first clock buffer for receiving an external clock signal through a non-inverting terminal of the first clock buffer and for receiving an external clock bar signal through an inverting terminal of the first clock buffer to thereby output a first clock input signal; a second clock buffer for receiving the external clock bar signal through the non-inverting terminal of the first clock buffer and for receiving the external clock signal through the inverting terminal of the first clock buffer to thereby output a second clock input signal; and a delay locked loop (DLL) for receiving the first clock input signal and the second clock input signal to thereby generate a duty corrected clock signal.

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Jong-Tae Kwak, et al., “A Low Cost High Performance Register-Controlled Digital DLL for 1Gbps×32 . DDR SDRAM”, 2003 Symposium on VLSI Circuits Digest of Technical Papers.

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