Delay-locked loop and a method of testing a delay-locked loop

Details Delay-locked loop and a method of testing a delay-locked loop Delay-locked loop and a method of testing a delay-locked loop

2008-04-01

2008-04-01

Nguyen, Vincent Q (Department: 2858)

Electricity: measuring and testing

Measuring, testing, or sensing electricity, per se

Frequency of cyclic current or voltage

C327S158000

Reexamination Certificate

active

11468955

ABSTRACT:
A delay-locked loop (DLL) of an integrated circuit (IC) with testing circuitry and a method for testing a DLL. During test mode, a phase comparator of the DLL receives a test clock in place of the reference clock and determines the phase difference between the test clock and the clock fed back to the DLL from a clock buffer tree. A variable delay element of the DLL then shifts the reference clock in time by an amount that depends on that phase difference. The variable delay element can be exercised by varying the phase of the test clock with respect to the reference clock by a known phase offset to cause the variable delay element to produce a range of delays. Whether the variable delay element is functioning properly can be determined by checking whether the phase of the test clock is aligned with the phase of the feedback clock.

REFERENCES:
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patent: 5717353 (1998-02-01), Fujimoto
patent: 6642701 (2003-11-01), Boateng
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Altera White Paper “The Need for Dynamic Phase Alignment In High Speed FPGAs” pp. 1-5. See also http://www.altera.com/literature/wp/wp—dpa.pdf.

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