Delay locked loop

Details Delay locked loop Delay locked loop

2002-06-20

2003-07-01

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S161000

Reexamination Certificate

active

06586978

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a delay locked loop that synchronizes an output clock with an input clock by delaying the input clock via a controllable delay path. The controllable delay time is set by a feedback loop containing a phase detector and a filter. The invention additionally relates to a method for operating such a delay locked loop.
A delay locked loop (DLL) is used in integrated circuits in order to synchronize an on-chip clock signal with a clock signal fed in externally. In today's electronic systems, for example in motherboards of personal computers, the various integrated circuits forming the system are operated clock-synchronously. Ever faster clock rates require that the specific timing specifications of the exchanged signals be complied with as exactly as possible. The available timing margins become smaller, so that the clock signals must be synchronized with one another as accurately as possible. A DLL has the task of carrying out this synchronization for a respective integrated circuit.
In particular, synchronously operating dynamic semiconductor memories, so-called SDRAMS (Synchronous Dynamic Random Access Memories) have a DLL which synchronizes an internal clock signal with a clock signal fed in from off-chip. The internally generated clock signal controls, for example, the time validation for the data signals that will be output. This compensates for the internal delay times of the fed-in clock signal on the semiconductor chip, so that the output data are present with a specific phase angle relative to the external operating clock. In the DLL, a phase detector determines the deviation between the external clock and the internal clock and accordingly readjusts the internal clock that is provided at the output of the DLL in a manner dependent on the external clock fed to the input of the DLL.
The filter, which sets the variable delay time of the delay path, ensures that the adjustment of the delay time by connecting in or disconnecting delay elements is not effective for every phase change that can occur in principle in every clock cycle. Previous filter concepts have the disadvantage that the delay time is adjusted only after the iteration of a fixed number of clock cycles. This number of clock cycles is independent of the phase difference between the input clock and the output clock. This means that the delay locked loop has different reaction times depending on the measure of the phase difference. The transient recovery time particularly in the case of a comparatively large phase difference that will be corrected is therefore relatively long.
U.S. Pat. No. 5,994,934 shows a delay locked loop having an external feedback loop and also an internal feedback loop that attaches to the loop filter and eliminates lock problems in the event of an excessive delay time (“Lock Deviation Phenomenon”). The delay locked loop otherwise has a delay circuit with a controllable delay time, a phase detector and also the loop filter.
U.S. Pat. No. 6,157,690 shows a digital phase locked loop in which the delay path can be controlled by a control circuit in order to effect an immediate phase shift, in the event of a comparatively large phase error, and a less rapidly executed phase correction in the event of a comparatively small phase error.
Published Japanese Patent Application JP 58-161426 shows the embodiment of a loop filter with flip-flops, shift registers and logic combination elements for a digital phase locked loop.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a delay locked loop and a method for operating the delay locked loop which overcomes the above-mentioned disadvantages of the prior art apparatus and methods of this general type.
In particular, it is an object of the invention to provide a delay locked loop whose transient recovery duration is always as short as possible.
With the foregoing and other objects in view there is provided, in accordance with the invention, a delay locked loop, including: an input for obtaining a signal to be delayed; an output for providing a delayed signal; and a delay circuit connected between the input and the output. The delay circuit has an output and a controllable delay time. The delay locked loop also includes a phase detector having an input coupled to the input for obtaining the signal to be delayed. The phase detector has another input coupled to the output of the delay circuit. The phase detector has an output. The delay locked loop also includes a filter having: a first input being controlled by the output of the phase detector; an output coupled to the delay circuit to control the delay time of the delay circuit; a multistage counter having counter stages connected between the first input and the output, and a second input. The delay locked loop also includes a control logic circuit for feeding back the output of the filter to the second input of the filter in order to control a number of the counter stages that are effective between the first input of the filter and the output of the filter.
In accordance with an added feature of the invention, the first input of the filter includes at least two inputs; the output of the filter includes at least two outputs; the at least two inputs of the filter and the at least two outputs of the filter are connected between the phase detector and the delay circuit; one of the at least two outputs of the filter is provided for increasing the delay time of the delay circuit; another one of the at least two outputs of the filter is provided for reducing the delay time of the delay circuit; the counter stages of the multistage counter of the filter include a first counter connected between a respective one of the at least two inputs of the filter and a respective one of the at least two outputs of the filter; and the counter stages of the multistage counter of the filter include a second counter connected between a respective one of the at least two inputs of the filter and a respective one of the at least two outputs of the filter.
In accordance with an additional feature of the invention, the control logic circuit includes an output; the first counter and the second counter each include at least a first stage having an output, a second stage having an input, and a changeover switch connected between the first stage and the second stage; the changeover switch is controlled by the output of the control logic circuit; the changeover switch has a first switch position in which the output of the first stage is coupled with the input of the second stage; and the changeover switch has a second switch position in which the output of the first stage is coupled with one of the outputs of the filter.
In accordance with another feature of the invention, an integrator for accumulating a number of pulses at the output of the filter; a comparison logic device for comparing the number of the pulses being accumulated by the integrator with a first reference value; and the comparison logic device, in a manner dependent on the comparing, controlling the number of the counter stages that are effective.
In accordance with a further feature of the invention, the first reference value is formed in a manner dependent on the number of the counter stages that are effective.
In accordance with a further added feature of the invention, the comparison logic device includes a counter for counting a number of pulses of the signal to be delayed; the comparison logic device includes a first comparator for comparing the number of the pulses that have been counted with a further reference value; the comparison logic device includes a second comparator for, in a manner prompted by the first comparator, comparing the number of the pulses at the output of the filter with the first reference value; and the number of the pulses at the output of the filter is generated by the integrator.
In accordance with a further additional feature of the invention, the number of the counter stages that are effective is reduced if a number of pulses

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