Delay locked loop

Details Delay locked loop Delay locked loop

2011-03-08

2011-03-08

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

Reexamination Certificate

active

07902889

ABSTRACT:
A delay locked loop includes a buffer for outputting an internal clock by buffering an external clock, a delay block for delaying the internal clock in response to one of control signals or a selection signal, thereby outputting a delayed clock, a control signal generation block for generating at least one control signal according to a phase difference between the internal clock and a feedback clock generated by delaying the delayed clock by a delay time taken for the internal clock to be output, a selection block for outputting at least one selection signal in response to a signal instructing an off mode of the delay locked loop, thereby controlling a delay time in the delay block, and an output driver for driving the delayed clock.

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Korean Office Action, with English Translation, issued in corresponding Korean Patent Application No. 9-5-2007-061185565, mailed on Nov. 19, 2007.
Korean Office Action, issued in Korean Patent Application No. 10-2006-0106781, dated on Feb. 1, 2008.

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