Delay locked loop

Details Delay locked loop Delay locked loop

2010-07-21

2011-12-20

Nguyen, Hai L (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S149000, C327S161000

Reexamination Certificate

active

08081021

ABSTRACT:
A semiconductor memory device includes a delay locked loop for achieving a delay locked state by correcting a phase difference between a reference clock and an internal delayed clock and for indicating the state that a larger delay amount than a maximum delay amount of a delay line is required, or a smaller delay amount than a minimum delay amount of delay line is required. A control unit resets the delay locked loop according to the state of the delay line.

REFERENCES:
patent: 6194930 (2001-02-01), Matsuzaki et al.
patent: 6316976 (2001-11-01), Miller et al.
patent: 6727739 (2004-04-01), Stubbs et al.
patent: 7777542 (2010-08-01), Ku
patent: 2001-0064123 (2001-07-01), None
patent: 2003-0048523 (2003-06-01), None
patent: 10-2004-0037797 (2004-05-01), None
patent: 10-2005-0097700 (2005-10-01), None

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