Delay locked loop

Details Delay locked loop Delay locked loop

1999-08-02

2001-04-10

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S161000, C327S270000, C327S271000

Reexamination Certificate

active

06215343

ABSTRACT:

The invention relates to a delay locked loop comprising a chain of at least two delay elements, of which a first delay element has an input for receiving a reference signal, and of which a last delay element has an output for delivering an output signal; a phase comparator having a first input for receiving the reference signal, a second input for receiving the output signal, and an output for delivering a binary control signal; and a converter for converting the binary control signal into an analog control signal for controlling a delay time of at least one of said delay elements.
Such a delay locked loop is known from the general state of the art. A purpose of the known delay locked loop is to create multiple output signals taken from the outputs of the delay elements, which output signals have a well-defined phase relationship with the reference signal. This well-defined phase relationship is accomplished that the phase comparator compares the phase of the output signal with the phase of the reference signal. The delay locked loop then controls the delay time of the delay elements in such a way that at the end the phase difference between the output signal and the reference signal substantially equals an integral multiple of 360 degrees.
A problem of the known delay locked loop is that it can easily happen that the delay locked loop locks at an undesired integral multiple of 360 degrees. Let it be assumed for example, that the desired phase difference between the output signal and the reference signal is 360 degrees (the multiple=1) and that for example, the desired phases of the output signals of the delay elements are 90 degrees, 180 degrees, and 270 degrees, respectively. If, however, the delay locked loop locks at a wrong integral multiple of 360 degrees, for example 720 degrees (the multiple=2), the afore-mentioned phases of the output signals of the delay elements are 180 degrees, 360 degrees, and 540 degrees, respectively which are not the desired phases.
It is an object of the invention to provide an improved delay locked loop which eliminates the above-mentioned disadvantage.
To this end, according to the invention, the delay locked loop of the type defined in the opening paragraph is characterized in that the phase comparator comprises at least one additional input for receiving an output signal of at least one of the delay elements preceding the last delay element.
The invention is based on the insight that the problem of the known delay locked loop is caused by the fact that the phase comparator only receives information from the reference signal and the output signal and does not receive additional information from one or more of the output signals of the delay elements not being the last delay element. Since the phase comparator of the delay locked loop according to the invention does receive additional information from one or more of the output signals of the delay elements not being the last delay element, it has become possible for the delay locked loop to lock in order to obtain the appropriate integral multiple of 360 degrees.
The delay locked loop is further characterized in that the phase comparator comprises a first basic flip-flop having a clock input coupled to the first input of the phase comparator, a data input, an output, and a reset input; a second basic flip-flop having a clock input coupled to the second input of the phase comparator, a data input, an output, and a reset input; an initialization flip-flop having a clock input coupled to the first input of the phase comparator, a data input for receiving a fixed data input state, an output coupled to the data input of the first basic flip-flop, and a reset input; a chain of flip-flops in which each flip-flop has a clock input forming the at least one additional input, which is coupled to an output of a corresponding delay element, an output, a data input coupled to the output of the preceding flip-flop, except for the data input of the first flip-flop, which data input is coupled to the output of the initialization flip-flop, and a reset input, and in which the output of the last flip-flop is coupled to the data input of the second basic flip-flop; and resetting means for supplying under command of signals on the outputs of the first and the second basic flip-flop, at least one reset signal to the reset inputs of the first and the second basic flip-flop, to the initialization flip-flop, and to the chain of flip-flops.
In this embodiment of the invention the state of the delay locked loop is initialized during a clock cycle of the reference signal by applying a reset signal to the reset inputs of the initialization flip-flop, the first and the second basic flip-flops, and the chain of flip-flops.
The state of the binary control signal delivered by the phase comparator is not solely determined by the reference signal and the output signal of the phase comparator, but also by the state of one or more output signals of the chain of flip-flops. This is accomplished by coupling the clock inputs of the chain of flip-flops to the outputs of corresponding delay elements. Thus the occurrences of subsequent active edges of the output signals of the delay elements are registered in the chain of flip-flops. These occurrences are in fact the additional information needed by the delay locked loop in order to determine the appropriate binary control signal from which the analog control signal for controlling the delay time of the delay elements is derived.
The delay locked loop is further characterized in that the number of flip-flops in the chain of flip-flops is equal to the number of delay elements minus one. Thus the above-mentioned occurrences of all the output signals of the delay elements are registered in the chain of flip-flops. This provides maximum robustness (i.e. reliability of the desired operation).
The required number of occurrences to be registered may be compromised with the potential robustness. This requires a trade-off with the number of required flip-flops in the chain of flip-flops.
The delay locked loop is further characterized in that the chain of flip-flops has been replaced by a single flip-flop. The advantage of this is that the required number of flip-flops, and thus the required chip-area when the invention is used in an integrated circuit, is hardly larger than in the case of a delay locked loop according to the prior art, while the robustness is still improved.


REFERENCES:
patent: 5179303 (1993-01-01), Searles et al.
patent: 5663665 (1997-09-01), Wang et al.
patent: 0609967A2 (1994-08-01), None

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