Delay locked loop

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Rectangular or pulse waveform width control

Reexamination Certificate

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Reexamination Certificate

active

07548100

ABSTRACT:
The digital duty cycle correction circuit according to the present invention includes a first conversion circuit for buffering an internal clock output from a delay locked loop (DLL), converting the buffered internal clock into first and second clocks through first and second terminals, delaying the second clock according to voltage supplied to the second terminal through a capacitor, converting the delayed second clock into a first signal, and converting the first clock into a third clock, which rises at a falling edge of the first clock and falls at a rising edge of the first signal; and a second conversion circuit for converting the third clock into an output clock, which rises at a falling edge of the third clock and falls at a rising edge of the third clock.

REFERENCES:
patent: 6342801 (2002-01-01), Shin
patent: 6566925 (2003-05-01), Ma
patent: 6831493 (2004-12-01), Ma
patent: 6859081 (2005-02-01), Hong et al.
patent: 6934215 (2005-08-01), Chung et al.
patent: 6963235 (2005-11-01), Lee
patent: 7106116 (2006-09-01), Yamada
patent: 7116143 (2006-10-01), Deivasigamani et al.
patent: 7215168 (2007-05-01), Takahashi et al.
patent: 2006/0114041 (2006-06-01), Koo
patent: 2006/0267649 (2006-11-01), Park et al.
patent: 2004-129255 (2004-04-01), None
patent: 2006-060842 (2006-03-01), None
patent: 1020040021478 (2004-03-01), None
patent: 1020050040551 (2005-05-01), None
Korean Notice of Allowance for 2006-36608.

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