Delay locked loop

Details Delay locked loop Delay locked loop

2007-07-09

2009-11-24

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S156000

Reexamination Certificate

active

07622968

ABSTRACT:
In a delay locked loop, a phase detector compares the phases of an input signal and an output signal; a delay line delays the input signal, wherein the delay line includes a plurality of unit delay elements connected in series and the value of the unit delay of each of the unit delay elements is adjusted by a control signal; a multiplexer selects a number of delay stages of the unit delay elements according to the phase comparison result and generates the output signal. The control signal is related to a clock information signal. When the input signal is high frequency, the value of the unit delay would be small; and when the input signal is low frequency, the value of the unit delay would be large.

REFERENCES:
patent: 6078864 (2000-06-01), Long et al.
patent: 6437619 (2002-08-01), Okuda et al.
patent: 6847241 (2005-01-01), Nguyen et al.
patent: 7157951 (2007-01-01), Morrison et al.
patent: 7202721 (2007-04-01), Jeon
patent: 7339407 (2008-03-01), Jakobs et al.
patent: 2003/0052718 (2003-03-01), Takai

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