Delay lock loop with transition recycling for clock recovery of

Details Delay lock loop with transition recycling for clock recovery of Delay lock loop with transition recycling for clock recovery of

1997-03-31

2000-02-22

Bocure, Tesfaldet

Pulse or digital communications

Synchronizers

Self-synchronizing signal

375375, H04L 702

Patent

active

060289031

ABSTRACT:
A clock recovery circuit uses a pair of variable delay lines to recover clock from a non-return to zero (NRZ) data stream. If an incoming clock transition occurs in the NRZ data, it is passed through one delay line to the output. If no incoming transition occurs, the transition at the output of the first delay line is recycled back through the second delay line. The outputs of the first and second delay lines are combined so that a transition occurs at every possible transition instant, regardless of whether a transition is present in the incoming data at the corresponding time. This permits the benefits of a delay locked loop to be achieved when using NRZ data. Applications of the clock recovery circuits to gigabit data communications systems are describe.

REFERENCES:
patent: 3790892 (1974-02-01), Tan et al.
patent: 4513427 (1985-04-01), Borriello et al.
patent: 5436938 (1995-07-01), Pigeon
patent: 5661419 (1997-08-01), Bhagwan
patent: 5771264 (1998-06-01), Lane
patent: 5875219 (1999-02-01), Kim
"Fiber Optic Minimun Component Count Clock Recovery Scheme", IBM Technical Disclosure Bulletin, vol. 31, No. 2, Jul. 1988, New York, pp. 169-170.
Beomsup Kim et al., "PLL/DLL System Noise Analysis for Low Jitter Clock Synthesizer Design", Proc. of the Intl. Symposium on Circuits and Systems, Jun. 1994.
Inyeol Lee et al., "A 622Mb/s CMOS Clock Recovery PLL with Time-Interleaverd Phase Detector Array", IEEE ISSCC Digest, pp. 198-199, 1996.
B. Razavi, Monolithic Phase-Locked Loops and Clock Recovery Circuits, IEEE Press, pp. 16-17, 1996.

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