Pulse or digital communications – Spread spectrum – Direct sequence
Reexamination Certificate
2001-02-08
2003-02-18
Ghebretinsae, Temesghen (Department: 2631)
Pulse or digital communications
Spread spectrum
Direct sequence
C375S141000, C375S376000
Reexamination Certificate
active
06522684
ABSTRACT:
FIELD OF THE INVENTION
The present invention in general relates to a delay lock loop (hereinafter, referred to as DLL) used for a direct spectrum spreading communication system. More particularly, this invention relates to a DLL which carries out a code synchronization tracking process between a spread code sequence which has been multiplied with a signal received from a transmitter and a spread code sequence used in a correlator of a receiver. This invention also relates to a receiver and a spectrum spreading communication system that uses such a DLL.
BACKGROUND OF THE INVENTION
A conventional DLL will be explained here. In recent years, in the field of mobile communication systems and satellite communication systems, research efforts have been focused on “a code-division multiple-connection communication system using a spectrum spreading system” as one of the transfer systems for images, voice, data, etc. Moreover, in the direct spreading system used in the following conventional technique, an information signal is directly multiplied by a spread code sequence having a band much wider than that of the information signal so that communications are carried out by using the spread information signal.
The conventional spectrum spreading communication system is disclosed, for example, in Japanese Patent Application Laid-Open No. HEI 6-197096. This application discloses Mobile Communication System (hereinafter, referred to as an offset multiplex SS system). In this offset multiplex SS system, parallel data is subjected to a spectrum spreading process by using the same spread code, a time offsetting process and a multiplexing process, and data communication is then carried out.
FIG. 10
shows a construction of a conventional DLL described in Japanese Patent Application Laid-Open No. 4-347944 that makes uses of the direct spreading system. Here, the DLL is a circuit used for tracking a code synchronization that is established between the transmitter side and the receiver side in the initial acquisition circuit. Moreover, in this description, the code synchronizing state refers to a state in which the spread code by which a receiving signal is multiplied and a spread code used in the correlator have the same phase at the time of data demodulation.
In
FIG. 10
, legends
111
and
112
denote square calculation sections, legend
113
denotes an adder, legend
114
denotes a delay section for adding a delay of time &dgr; (0<&dgr;≦2T
c
) to an inputted signal,
115
is a subtraction section,
116
is a latch section,
117
is a loop filter,
118
is a voltage control generator (hereinafter, referred to as VCC) which changes a timing phase of a clock having a frequency band that is M times the chip rate R
c
by using an error signal that has been filtered so as to generate a sample clock,
119
is a data clock generation section, and
120
is a delay section for adding a delay of time &dgr;/2 to the inputted signal.
Operation of the conventional DLL will be explained here. A case is assumed in which the number of multiplexing N is equal to 1 and the delay coefficient &tgr;
1
is equal to 0. In the conventional DLL, first, the square calculation sections
111
and
112
respectively output values obtained by squaring an in-phase correlation signal and an orthogonal correlation signal. The adder
113
adds the in-phase correlation signal thus squared and the orthogonal correlation signal thus squared so that a correlation electric power obtained as a result of the addition is outputted. Moreover, in the subtraction section
115
, the correlation power outputted by the adder
113
is subtracted from a correlation power to which the delay is added in the delay section
114
so that an error signal indicating an advance/delay of the timing phase of the sample clock is generated.
In the data clock generation section
119
, based upon an acquisition pulse synchronous to the cycle T
p
of a spread code sequence by which the multiplex RF signal is multiplied, the sample clock is frequency-divided so that a data clock that has a rising edge in synchronized timing with a peak of the correlation power with a clock cycle of T
p
is generated.
In the latch section
116
, the above-mentioned error signal is latched at the rising edge of the data clock to which a delay of time &dgr;/2 has been added in the delay section
120
. Then, the loop filter
117
carries out a filtering process on the latched error signal so that noise components are eliminated, thereby making it possible to generate an error signal having a high S/N ratio. Finally, in the VCC
118
, the timing phase of the clock having a frequency band that is M times that of the chip rate R
c
is changed based upon the error signal after having been subjected to the filtering process that is outputted from the loop filter
117
so that a sample clock is generated.
The operation of the conventional DLL will be explained with the help of mathematical equations. For example, assuming that a transmitting carrier angular frequency is &ohgr;
c
, a digital information signal at time t is D(t), the code length is L, the chip frequency is T
c
and a PN signal having the code frequency LT
c
is represented by c (t), the receiving RF signal f(t) is represented by the following equation (1):
f
(
t
)
=D
(
t
)
c
(
t
) cos (&ohgr;
c
t
)+
jD
(
t
)
c
(
t
) sin (&ohgr;
c
t
) (1)
Here, it is assumed that the frequency of a local carrier generated in a voltage control carrier generator (hereinafter, referred to as VCO) used in this receiver has the same value &ohgr;
c
as a transmission carrier angular frequency. Therefore, assuming that the in-phase component (the in-phase component of a complex spectrum spreading signal) that has been subjected to a quadrature detecting process by the receiver is a signal I(t), the signal I(t) is represented by the following equation (2):
I
(
t
)
=D
(
t
)
c
(
t
) cos (&Dgr;&thgr;) (2)
(where &Dgr;&thgr; is a carrier phase difference between the transmitter and receiver).
In the same manner, assuming that the orthogonal component (the orthogonal component of the complex spectrum spreading signal) that has been subjected to a quadrature detecting process by the receiver is a signal Q(t), the signal Q(t) is represented by the following equation (3):
Q
(
t
)
=D
(
t
)
c
(
t
) sin (&Dgr;&thgr;) (3)
Moreover, in the receiver, an in-phase correlation signal SI (t) and an orthogonal correlation signal SQ(t) are found from the in-phase component I(t) and the orthogonal component Q(t) that have been subjected to the quadrature detecting process. The in-phase correlation signal SI(t) and the orthogonal correlation signal SQ(t) are respectively represented by the following equations (4) and (5):
SQ
(
t
)
=
∑
k
=
0
L
-
1
Q
(
t
+
kT
c
)
c
(
kT
c
)
=
∑
k
=
0
L
-
1
D
(
t
+
kT
c
)
sin
(
Δ
θ
)
c
(
t
+
kT
c
)
c
(
kT
c
)
(
5
)
Therefore, in the calculation section
113
, the correlation power SP(t) is found from the following equation (6):
SP
(
t
)={
SI
(
t
)}
2
+{SQ
(
t
)}
2
SP
(
t
)
=
{
SI
(
t
)
}
2
+
{
SQ
(
t
)
}
2
=
{
∑
k
=
0
L
-
1
D
(
t
+
kT
c
)
c
(
t
+
kT
c
)
c
(
kT
c
)
}
2
(
6
)
Here, in the case when the initial acquisition has been carried out completely at time &agr;, the digital information signal D (&agr;+kT
c
) has no transition point in data during the correlation operation (k=0, 1, 2, . . . , L−1) Moreover, it is assumed that the time at which the code synchronization has been achieved completely is indicated by &agr;=0. For this reason, in the correlation operation, D (&agr;+kT
c
) takes a constant value of “1” or “−1”, and the correlation power SP(&agr;) is represented by the following equation (7).
SP
(
α
)
=
{
∑
k
=
0
L
-
1
c
(
α
+
kT
c
)
c
(
kT
c
)
}
2
=
{
{
L
-
(
L
+
1
)
&LeftBracketingBar
Fujimura Akinori
Kojima Toshiharu
Okubo Seiji
Birch & Stewart Kolasch & Birch, LLP
Ghebretinsae Temesghen
Mitsubishi Denki & Kabushiki Kaisha
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