Delay lock loop circuit, variable delay circuit, and...

Details Delay lock loop circuit, variable delay circuit, and... Delay lock loop circuit, variable delay circuit, and...

2002-02-25

2004-05-04

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S160000

Reexamination Certificate

active

06731144

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a delay lock loop circuit for providing a desired signal delay amount, a variable delay circuit having the delay lock loop circuit, and a recording signal compensating circuit having this variable delay circuit.
Optical-disk-based high-density recording systems under development include a magneto-optical disk system and a phase change optical disk system. In the latter, information is recorded by changing a recording layer to a crystalline phase or an amorphous phase. Recently trend is a particular emphasis on the development of this phase change optical disk system because of its ease of making the optical head smaller because no magnetic head is used, its ease of realizing direct overwriting by which information can be recorded by a single laser irradiation regardless of the presence or absence of marks on the recording surface, and its ease of increasing the S/N (Signal to Noise) ratio of the reproduction system due to a high signal strength, for example.
In a high-density optical disk system, microscopic mark trains must be recorded in correct positions. In the case of the phase change optical disk, signal recording is pure thermal recording, so that heat control at recording is very important for the correct formation of marks. For example, if a recording-level laser is irradiated for a relatively long time to form a comparatively long mark, the formed mark becomes wider toward its end in the disk radius direction due to the thermal storage effect of the recording film. If such a mark is formed, the edge of the trailing end is offset from an ideal position, resulting in an increased error rate. For this reason, the phase change optical disk system uses continuous pulse trains as a laser for mark formation for the thermal control at recording. Also, it is essential for the phase change optical disk system to perform so-called recording compensation to optimally set not only the pulses synchronized with clock but also the position and width of each mark.
One example of the data recording apparatus which performs such recording compensation is disclosed in Japanese Patent Laid-open No. Hei 10-091961. In this disclosure, recording pulses are generated in which a leading pulse having length
1
.
5
T is followed by a pulse train synchronized with clock, thereby lowering the amount of irradiation in the last half of each mark to prevent its width from getting larger. However, this makes the end portion of each mark thermally unstable, sometimes failing to form marks at correct positions. To prevent this problem from happening, the rising edge position and the falling edge position of pulse are delayed to vary the pulse widths of the leading pulse and the trailing pulse. In the disclosed data recording apparatus, such recording pulse B is obtained by a normal logic circuit and a recording compensation circuit based on a delay element of variable delay amount type.
For a delay element for delaying an input signal, an all-pass filter formed by an LC (inductor and capacitor) or a distribution constant circuit for example is known. The delay element of delay amount variable type includes one in which two or more LC delay elements are connected in series, selecting the output from each element by a selector. The delay element having his configuration can provide a comparatively stable delay amount, but presents a problem of significantly increasing the element unit price as compared with the ICs (Integrated Circuits) based on CMOS (Complementary Metal-Oxide Semiconductor) process if the element itself grows in dimension, thereby requiring a larger packaging area. Also, a method is available in which the delay element of delay amount variable type which can be incorporated in a CMOS IC for example is realized by use of the frequency multiplication capability of PLL (Phase-Locked Loop). This method can solve the problem of the large packaging area by incorporating the delay element in the IC but still presents a problem of the increased cost due to the PLL incorporation.
On the other hand, developed with application to digital integrated circuits such as gate arrays and embedded arrays in mind is a delay element realized by positively using the signal propagation delay time in CMOS logic by use of a combination of buffers formed by inverter and NAND gate. Such a delay circuit is obtained by connecting delay lines with two steps of inverters connected in series by the number of steps in series so that a desired delay amount is obtained, for example. The delay circuit having this structure can be configured by basic logic elements, so that it can be easily incorporated in a CMOS IC, thereby involving little increase in packaging area and cost. At the same time, the delay amount generated by the gates inside the IC fluctuates as largely as three times depending on the fluctuations in temperature and supply voltage and the process conditions for example.
For the purpose of solving the above-mentioned problems of CMOS-logic-based delay circuits, a variable delay circuit is disclosed in Japanese Patent Laid-open No. Hei 2000-134072 in which a delay lock loop circuit is used to adjust the number of delay line steps for obtaining a delay amount for
1
T. Now, referring to
FIG. 15
, there is shown a block diagram illustrating an exemplary configuration of a delay lock loop circuit used in the disclosed variable delay circuit.
A delay lock loop circuit
40
shown in
FIG. 15
includes a divider
41
for dividing an input pulse into a predetermined frequency and outputting the resultant pulse, a delay line
42
capable of providing a desired delay amount by varying the number of delay steps, a delay amount detector
43
for determining which of input pulses has come first and, on the basis of the decision, outputting a control signal, an up/down counter (hereafter referred to as a U/D counter)
44
for controlling the number of delay steps in the delay line
42
in accordance with this control signal, and a delay lock detector
45
for outputting the number of delay steps which provide the amount of delay of
1
T provided by the delay line
42
with reference to the output signal of the U/D counter
44
.
The divider
41
generates data pulse TP of
1
T obtained by dividing inputted clock CLK by 2, data pulse TP
2
of
2
T obtained by dividing CLK by 4, and data pulse TP
4
of
4
T obtained by dividing CLK by 8. The delay line
42
is a signal delay circuit which is formed by two inverters for example connected in series which are connected in series by the required number of steps, thereby providing variable delay amounts. With count value SEL of the U/D counter
44
used as the setting data for the number of delay steps, the delay line
42
delays, by
1
T, data pulse TP supplied from the divider
41
. The delay amount detector
43
outputs, on the basis of data pulse DTP delayed by the delay line
42
and data pulse TP
2
supplied from the divider
41
, an up/down control signal (hereafter referred to as a U/D control signal) UD for controlling the count-up and count-down operations of the U/D counter
44
.
Referring
FIG. 16
, there is shown a circuit diagram illustrating an exemplary circuit configuration of the delay amount detector
43
.
The delay amount detector
43
includes a D flip-flop (hereafter referred to as a D-FF)
431
forming an input stage, an exclusive OR gate (hereafter referred to as an EOR gate)
432
, an inverter
433
, and a D-FF
434
forming an output stage. In this delay amount detector
43
, the D-FF
431
latches data pulse TP
2
supplied from the divider
41
on the basis of data pulse DTP outputted from the delay line
42
to determine which of the rising of data pulse DTP delayed by
1
T by the delay line
42
and the inversion of data pulse TP
2
providing reference of timing for delay amount
1
T has come first. On the basis of the result of the decision, the delay amount detector
43
outputs, from the D-FF
434
, a U/D control signal UD as a control signal for selecting the increase or decrease in t

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