Delay lock loop circuit, timing generator, semiconductor...

Details Delay lock loop circuit, timing generator, semiconductor... Delay lock loop circuit, timing generator, semiconductor...

2006-10-18

2011-11-15

Velez, Roberto (Department: 2858)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

Reexamination Certificate

active

08058891

ABSTRACT:
A delay lock loop circuit and its delay amount calibration method is disclosed. An initially set value of a counter is determined by a technique which replaces measurement of a delay amount, whereby a time required for calibration of a delay circuit can be reduced. One counter set value of a plurality of counter set values is loaded, a delay lock loop circuit is switched to a lock mode, and a sequence circuit of a cycle slip detection circuit is reset. Thereafter, a cycle slip detection signal output from the sequence circuit is read, and based on the reading, it is judged whether or not an output signal of a delay circuit causes cycle slip. If the cycle slip is caused, the counter set value is switched. If any cycle slip is not caused, the counter set value is locked, thereby terminating the process.

REFERENCES:
patent: 6466058 (2002-10-01), Goldman
patent: 2004/0247066 (2004-12-01), Suda
patent: 09-23157 (1997-01-01), None
patent: 2003-69425 (2003-03-01), None
patent: 2004-350116 (2004-12-01), None
patent: 2005-20711 (2005-01-01), None
patent: 2005-51673 (2005-02-01), None
patent: WO 03/036796 (2003-05-01), None
patent: WO 03-036796 (2003-05-01), None

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