Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
1999-09-20
2001-06-05
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S284000
Reexamination Certificate
active
06242955
ABSTRACT:
FIELD OF INVENTION
The present invention relates to clock synchronizing circuits and more particularly, to a circuit method and system for synchronizing an output clock signal with an input reference clock signal.
BACKGROUND OF THE INVENTION
The problem of providing clock regeneration systems in semiconductor memory devices which will achieve stable lock in the shortest time, irrespective of whether the phase of a local clock signal is leading or lagging relative to the phase of a reference signal, has been a major challenge to designers in the high speed computer field. The regeneration must be performed at all sites in the computer so that all regenerated clock signals are produced with minimum skew. Current telecommunication and graphics applications such as pixel clock generation require high resolution, fast lock-in times and a wide frequency range. Furthermore, DDR DRAM circuits require the minimum phase delay time to be less than one-half period of the reference signal.
Delay Lock Loop (DLL) circuits have become a critical part in solving this electronic system timing problem. In particular, DLLs allow designers to monitor the phase difference between a reference signal and an internal clock signal, relative to the reference signal. This phase difference between the reference signal and the internal clock signal results in a corresponding response delay in the semiconductor memory device. Consequently DLLs are utilized to align the reference signal with the internal clock signal. There are three types of DLLs: digital, analog, and hybrid.
FIG. 1
shows a conventional digital delay locked loop (D-DLL) configuration. A D-DLL consists of a phase detector
12
which measures the phase difference between an input reference signal
10
and an internal timing signal. The phase detector
12
drives a shift register
14
which causes the stored data to move to the right or left one bit position based on the difference in the signals. The shift register
14
is coupled to a delay line
16
for producing a phase-adjusted clock signal
20
by sequentially delaying the internal timing signal in accordance with the shift register
14
. When the reference signal
10
and the internal timing signal are identical, the DLL is “locked” onto the reference signal. A clock buffer circuit
18
simply buffers the phase-adjusted clock signal
20
prior to output.
This kind of DLL is simple to implement and will be locked-in very quickly but has several drawbacks. Resolution is not very high and the minimum phase difference will change when operation conditions (i.e. supply voltage, temperature) change. Also, a long delay line is needed to achieve a reasonable resolution and cover a wider frequency range while a large shift register is needed to control the switch inside the delay line.
FIG. 2
shows a conventional analog delay locked loop (A-DLL) configuration. This type of DLL configuration consists of a phase-frequency detector
32
which measures the phase and frequency difference between an input reference signal
30
and an internal timing signal. The phase-frequency detector
30
then supplies a phase difference detection signal, based on the phase difference between the two signals, which generates a direct control voltage to a delay line
34
through the current controller
36
which includes a charge pump and a low pass filter (LPF)
33
. The delay line
34
then develops an internal timing signal that is fed back to the phase-frequency detector for comparison with the reference signal
30
. Again, when the reference signal
30
and the internal timing signal are identical, the DLL is locked onto the reference signal
32
. This type of DLL delivers a high resolution but consequently has a very long lock-in time.
There are ways to build hybrid DLLs which have both digital and analog delay controls.
FIG. 3
shows the architecture of a conventional hybrid DLL
50
containing digital delay controls
52
and analog delay controls
54
. However, conventional hybrid DLLs employ a large shift register
56
and normally exhibit phase jump problems when tracking an internal clock signal because the digital delay controls may keep shifting before the analog delay controls can respond. Also, the implementation of solid control circuits for conventional hybrid DLLs is difficult and typically these DLLs do not cover a large frequency range.
What is needed is a hybrid DLL that will provide faster lock-in times, cover a large frequency range, while also providing a high resolution. The present invention addresses such a need.
SUMMARY OF THE INVENTION
A method and system for synchronizing a reference signal and an output signal produced by an electrical circuit, the electrical circuit comprising an analog portion and a digital portion, is disclosed. The method comprises the steps of utilizing the digital portion to produce a phase-adjusted signal and utilizing the analog portion to produce an output signal in substantially the same phase as the phase-adjusted signal.
Through the use of the method and system in accordance with the present invention, the large bi-direction shift register of conventional hybrid DLLs is no longer necessary and high speed DLLs will be capable of providing high resolution deskewed clocks in a shorter amount of time. The use of the present invention also facilitates the coverage of a wider range of clock frequencies.
REFERENCES:
patent: 4847870 (1989-07-01), Butcher
patent: 5487093 (1996-01-01), Adresen et al.
Shen Fang
Wang Chen
Cox Cassandra
Sawyer Law Group LLP
Silicon Magic Corporation
Tran Toan
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