Delay lock loop

Details Delay lock loop Delay lock loop

1998-11-25

2000-10-24

Le, Dinh T.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327149, H03L 706

Patent

active

061373273

ABSTRACT:
A delay lock loop circuit, in accordance with the present invention, includes a receiver for receiving a system clock signal and outputting a first clock signal derived from the system clock signal, a delay lock loop for receiving the first clock signal, the first clock signal for synchronizing the delay lock loop and a phase detector and an off chip driver circuit for receiving the first clock signal and outputting data in accordance with a second clock signal derived from the first clock signal. A feedback loop is provided coupling the off driver circuit to the phase detector. The feedback loop includes an on chip delay circuit for modeling on chip delay and a package delay circuit for modeling chip package delay. The feedback loop provides synchronization between the system clock signal and the data output from the off chip driver circuit.

REFERENCES:
patent: 5355037 (1994-10-01), Andresen et al.
patent: 5663665 (1997-09-01), Wang et al.

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