Delay lock code tracking loop employing multiple timing...

Pulse or digital communications – Spread spectrum – Direct sequence

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C375S354000

Reexamination Certificate

active

06901106

ABSTRACT:
A code tracking system and method especially for use in direct sequence code division multiple access (DS-CDMA) communication systems employs multiple timing references within a chip by tracking the multiple timing references relative to the exact midpoint of the chip, then adjusting the timing references to the exact midpoint of the chip, and outputting an error tracking signal in accordance with the minimum error associated with the multiple timing references. The system performs effective code tracking with low lock-loss rate even when the noise of a receiving path interferes with detection of some of the timing references. The system uses multiple delay-locked loops for the different timing references.

REFERENCES:
patent: 5299229 (1994-03-01), Zscheile, Jr. et al.
patent: 5737362 (1998-04-01), Hyun et al.
patent: 6154487 (2000-11-01), Murai et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Delay lock code tracking loop employing multiple timing... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Delay lock code tracking loop employing multiple timing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Delay lock code tracking loop employing multiple timing... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3429895

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.