Delay lock circuit using bisection algorithm and related method

Details Delay lock circuit using bisection algorithm and related method Delay lock circuit using bisection algorithm and related method

2005-05-31

2005-05-31

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S159000, C327S277000

Reexamination Certificate

active

06900678

ABSTRACT:
A method for performing a delay lock to generate a second clock according to a first clock and to synchronize the second clock with the first clock is provided. The method has correcting processes executed to increase or decrease, by a correction interval, a delay time between corresponding periods of the first clock and the second clock. The correction interval for a subsequent correcting process is substantially half the previous correction interval of the previous correcting process.

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patent: 6483359 (2002-11-01), Lee
patent: 6489823 (2002-12-01), Iwamoto
patent: 199813219 (1998-01-01), None

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