Delay line with delay cells having improved gain and in...

Details Delay line with delay cells having improved gain and in... Delay line with delay cells having improved gain and in...

2007-06-10

2009-06-16

Luu, An T (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S263000, C327S264000, C327S285000

Reexamination Certificate

active

07548104

ABSTRACT:
A delay line including a sequence of identical delay cells with improved gain and in built duty cycle distortion control and a method thereof is disclosed. Each delay cell of the sequence includes a current source, four transistors, and a load capacitor. A gate of the current source receives a voltage bias that controls a delay of the delay cell. A drain of the first transistor is connected to the drain of the current source. The first and second transistor gates receive an input clock signal. The second transistor drain is connected to the source of the current source. The third transistor gate and the load capacitor are also connected to the drain of the current source. The fourth transistor drain is connected to the third transistor drain. The fourth transistor gate is coupled to an output of a second consecutive delay cell for duty cycle distortion control.

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