Delay line separator for data bus

Pulse or digital communications – Synchronizers – Self-synchronizing signal

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375371, 327284, H04C 702, H04C 700

Patent

active

056195419

ABSTRACT:
The delay line separator extracts a clock signal from a combined data/clock encoded signal received over a serial data bus, despite the presence of significant duty cycle distortion. Such distortion affects the width of symbols within received data packets but does not affect the timing between successive rising edges within the received pulse string. To extract the chock signal from the distorted signal, the separator exploits a pre-filter circuit which generates 2 -nanosecond pulses synchronized with each rising edge in the received signal. A 20-nanosecond pulse train is transmitted down a delay line having twelve delay elements. Circuits are connected to every other delay element within the delay line for generating 10-nanosecond pulses, synchronized with each rising edge of the pulse train. Outputs from the circuits are combined using an OR gate to yield a 10-nanosecond clock signal. The pre-filter generates 20-nanosecond pulses, rather than 10-nanosecond pulses, to ensure that the pulses successfully propagate the entire length of the delay line, despite the presence of significant dispersion within each delay element. Additional circuits are tapped into the delay elements, as desired, to generate additional clock signals delayed by 5- or 10-nanosecond intervals.

REFERENCES:
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patent: 5412697 (1995-05-01), Van Brunt et al.
patent: 5412698 (1995-05-01), Van Brunt et al.
"Digital Communications Fundamentals and Applications" Bernard Shlar, Prentice Hall, 1985, pp. 78-82.

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