Delay line separator for data bus

Details Delay line separator for data bus Delay line separator for data bus

1993-01-14

1995-05-02

Chin, Stephen

Pulse or digital communications

Synchronizers

Self-synchronizing signal

375376, 327 98, 327284, H04L 702, H03D 324

Patent

active

054126975

ABSTRACT:
The delay line separator extracts a clock signal from a combined data/clock encoded signal received over a serial data bus, despite the presence of significant duty cycle distortion. Such distortion affects the width of symbols within received data packets but does not affect the timing between successive rising edges within the received pulse string. To extract the clock signal from the distorted signal, the separator exploits a pre-filter circuit which generates 20-nanosecond pulses synchronized with each rising edge in the received signal. A 20-nanosecond pulse train is transmitted down a delay line having twelve delay elements. Circuits are connected to every other delay element within the delay line for generating 10-nanosecond pulses, synchronized with each rising edge of the pulse train. Outputs from the circuits are combined using an OR gate to yield a 10-nanosecond clock signal. The pre-filter generates 20-nanosecond pulses, rather than 10-nanosecond pulses, to ensure that the pulses successfully propagate the entire length of the delay line, despite the presence of significant dispersion within each delay element. Additional circuits are tapped into the delay elements, as desired, to generate additional clock signals delayed by 5- or 10-nanosecond intervals.

REFERENCES:
patent: 4435687 (1984-03-01), Nadan et al.
patent: 4513427 (1985-04-01), Borriello et al.
patent: 4805197 (1989-02-01), Van Der Jagt et al.
patent: 4841551 (1989-06-01), Avaneas

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