Demodulators – Frequency modulation demodulator – Input signal split into plural signals
Patent
1998-02-19
1999-11-23
Grimm, Siegfried H.
Demodulators
Frequency modulation demodulator
Input signal split into plural signals
329341, 329342, 375324, 455214, H03D 302
Patent
active
059907339
ABSTRACT:
An integrated circuit includes a demodulator having delay circuitry and demodulation control circuitry that may be fully formed within a common integrated circuit. The delay circuitry receives an input signal and generates a delayed input signal. The demodulation control circuitry generates a demodulated output based upon the input signal and the delayed input signal that has a level that is proportional to, or a finction of, a period of a respective cycle of the input signal. The demodulation control circuitry includes pulse generation circuitry, pulse delay circuitry, pulse conversion circuitry and sampling circuitry. The pulse generation circuitry generates a signal pulse based upon the input signal and the delayed input signal with a duration that is proportional to at least one period of the input signal. The pulse delay circuitry generates a delayed signal pulse based upon the signal pulse. The pulse conversion circuitry generates a converted signal that has a level based upon the duration of the signal pulse. The sampling circuitry samples the converted signal based upon a sample pulse to generate the demodulated output based upon the level of the converted signal. The delay circuitry and pulse delay circuitry each include a plurality of cascaded semiconductive elements that, in combination, produce a desired delay duration.
REFERENCES:
patent: 4603301 (1986-07-01), Dukes et al.
patent: 4988960 (1991-01-01), Tomisawa
patent: 5053717 (1991-10-01), Schulz et al.
patent: 5345188 (1994-09-01), Owen
Mahany Ronald L.
Schuster Thomas J.
Grimm Siegfried H.
Intermec IP Corp.
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